Fan-Out Wafer Level Package Structure

• US 20140110856A1
• Filed: 10/19/2012
• Published: 04/24/2014
• Est. Priority Date: 10/19/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng
• Granted Patent: US 9,391,041 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

Claims

1. A method for forming a package structure, comprising:

applying a die over a carrier, the die having a plurality of mounts;

providing one or more vias on the carrier;

forming a molded substrate over the carrier and around the vias;

reducing a first side of the molded substrate opposite the carrier and exposing the one or more vias at a first side of the molded substrate opposite the carrier;

forming a redistribution layer (RDL) on the first side of the molded substrate, the RDL having a plurality of RDL contact pads; and

exposing the one or more vias at a second side of the molded substrate opposite the first side.

2. The method of claim 1, wherein the molded substrate comprises an adhesive layer, wherein the die is applied to the adhesive layer and wherein the molded substrate is formed on the adhesive layer.

3. The method of claim 2, wherein the providing one or more vias on the carrier comprises applying one or more via chips to the adhesive layer, each via chip having one or more vias and at least one dielectric layer disposed in the via chip to separate the one or more vias, wherein the via chips are formed prior to applying the via chips to the adhesive layer.

4. The method of claim 1, wherein the reducing the first side of the molded substrate further comprises exposing the plurality of mounts on the die.

5. The method of claim 1, wherein the forming the RDL further comprises forming the RDL contact pads with a bond pitch greater than a bond pitch of the plurality mounts on the die.

6. The method of claim 1, further comprising mounting a second structure at the second side of the molded substrate, the second structure having at least one die disposed thereon and in electrical communication with at least one via.

7. A method for forming a package structure, comprising:

providing a carrier having an adhesive on a first side of the carrier;

applying a die on the adhesive, the die having a plurality of mounts;

providing vias on the adhesive;

forming a molded substrate over the carrier and around the die and the vias;

forming a redistribution layer (RDL) on a first side of the molded substrate, the RDL having a plurality of RDL contact pads and at least one conductive line;

applying a plurality of package mounts on the RDL contact pads; and

mounting a second structure over the die and on the vias.

8. The method of claim 7, wherein the providing the vias comprises providing one or more via chips on the adhesive, each via chip comprising at least one via.

9. The method of claim 8, wherein the providing the one or more via chips comprises forming the one or more via chips separate and away from the carrier and adhesive layer and prior to a placement of the one or more via chips on the adhesive layer.

10. The method of claim 8, wherein the one of the one or more via chips further comprise a dielectric layer separating the vias from the molded substrate, the dielectric layer comprising a material different from the molded substrate.

11. The method of claim 8, further comprising providing at least two via chips on the adhesive, wherein the die is disposed between the at least two via chips.

12. The method of claim 8, wherein the applying the die comprises providing at least two dies on the adhesive where at least one of the one or more via chips is disposed between the at least two dies.

13. The method of claim 8, wherein the second structure comprises at least one active device and wherein the at least one active device is in electrical communication with at least one of the plurality of RDL contact pads by way of at least one of the vias.

14. A package comprising:

a molded substrate;

a die having at least one mount, the die at least partially disposed within the molded substrate;

at least one via disposed within the molded substrate and having a first end at a first side of the molded substrate and a second end at a second side of the molded substrate opposite the first side; and

a first redistribution layer (RDL) formed on the first side of the molded substrate, the RDL having a plurality of RDL contact pads and a plurality of conductive lines in electrical contact with the RDL contact pads.

15. The package of claim 14, wherein the at least one mount of the die and the first end of the at least one via are exposed through the first side of the molded substrate.

16. The package of claim 15, wherein the first end of the at least one via and the at least one mount of the die are substantially planar with the first side of the molded substrate, and wherein the second end of the at least one via is substantially planar with the second side of the molded substrate.

17. The package of claim 14, wherein the molded substrate has a thickness about the same as a height of the die.

18. The package of claim 14, further comprising a second structure having at least one active device and mounted at the second side of the molded substrate, the active device in electrical communication with at least one of the vias.

19. The package of claim 14, wherein the at least one via is disposed within at least one via chip, the at least one via chip comprising a dielectric layer separating the vias from the molded substrate.

20. The package of claim 14, wherein the plurality of RDL contact pads have a bond pitch greater than a bond pitch of the at least one of the mounts of the die, and wherein at least one of the plurality of RDL contact pads is in electrical contact with a mount of the die.