METHOD AND APPARATUS FOR TESTING INTERCONNECTION RELIABILITY OF A BALL GRID ARRAY ON A TESTING PRINTED CIRCUIT BOARD

• US 20140111242A1
• Filed: 10/24/2012
• Published: 04/24/2014
• Est. Priority Date: 10/24/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Xie, Dongji, Woo, Min
• Granted Patent: US 9,329,227 B2
• Time in Patent Office: Days
• US Class Current: 324/762.02
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/71 Testing of solder joints
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit is presented. The assembly comprises a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon. Vias extend through the testing PCB from a surface to an underside thereof within the IC test region. Each via has an IO pad or ground pad electrically connectable thereto. An IC package having an IC die connected thereto by solder bumps is connected to the IC test region by solder balls, such that each of the IO pads is electrically connectable to a respective pair of the solder balls and solder bumps by the vias. A method of testing interconnection reliability of the BGA using the apparatus is also presented.

Claims

1. A method of determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit, comprising:

electrically connecting a integrated circuit (IC) package, having an IC die connected thereto by solder bumps, to an IC test region of a testing printed circuit board (PCB) by forming solder balls between bond pads of said IC package substrate and said testing PCB, said testing PCB having IO and ground pads located on an underside thereof and within said IC test region, wherein each of said IO and ground pads is electrically connectable, respectively, to different pairs of said solder bumps and solder balls;

stressing said IC package; and

determining an reliability of either or both of a solder bump and solder ball of at least one of said pair of solder bumps and solder balls, subsequent to said stressing, by contacting said IO and ground pads electrically connectable to respective pairs said solder bumps and solder balls.

2. The method of claim 1, wherein said stressing includes thermal cycling said IC package.

3. The method of claim 2, wherein thermal cycling includes generating a current through said IC die and said at least one of said pair of solder bumps and solder balls by applying a current to said IO pad that is connected to said ground pad.

4. The method of claim 1, wherein said ground pad is a reference ground and determining includes measuring a resistance of an electrical path between a solder bump connected to said reference ground pad and a solder ball connected to an IO pad.

5. The method of claim 1, wherein determining includes measuring a resistance of an electrical path between said IC die and said at least one of said pair of solder bumps and solder balls.

6. The method of claim 1, wherein said testing PCB includes a plurality of said IC testing regions and said method further includes electrically connecting one of said IC packages to each of said plurality of said IC testing regions and determining an electrical reliability of each of said IC packages.

7. The method of claim 1, wherein stressing includes repeatedly generating a current through said IC die for a pre-determined amount of time to ramp a temperature of said IC die up to at least an operating temperature of said IC die, maintaining said temperature for a pre-determined amount of time, and allowing said IC die to cool.

8. The method of claim 1, wherein said testing PCB includes an electrical pin connector mounted to a surface of said testing PCB and electrically connectable to pre-determined IO pads within said IC die region, and determining an electrical reliability includes determining a reliability of at least one of said pair of said solder bumps or solder balls that is electrically connectable to said electrical pin connector.

9. The method of claim 8, wherein said testing PCB includes a plurality of said IC die regions, each having an electrical pin connector electrically connectable thereto.

10. The method of claim 9, wherein said plurality of said IC die regions is configured to receive a different IC package thereon.

11. A method of determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit, comprising:

stressing an integrated circuit (IC) package electrically connectable to a testing printed circuit board (PCB) by solder balls, said IC package having an IC die electrically connectable thereto by solder bumps, said testing PCB having IO and ground pads located on an underside thereof and within an IC test region, wherein each of said ground and IO pads is respectively, electrically connectable to a different pair of said solder balls and solder bumps; and

testing an electrical continuity of said solder balls and solder bumps of said IC package after said IC package is stressed by applying a current through said IO to ground pads or through ground to ground pads connected to said different pairs of said solder balls and solder bumps.

12. The method of claim 11, wherein said stressing includes thermal cycling said IC package or subjecting said IC package to a physical stress.

13. The method of claim 12, wherein thermal cycling includes generating a current through said IC die by contacting an IO pad and a ground pad, respectively connected to respective pairs of solder balls and solder bumps.

14. The method of claim 11, wherein said ground pad is a reference ground pad and testing includes measuring a resistance of an electrical path between a solder ball connected to said reference ground pad and a solder bump of said at least one of said pair of solder balls and solder bumps, or wherein testing includes measuring a resistance of an electrical path between said IC die and said at least one of said pair of solder balls or solder bumps.

15. The method of claim 11, wherein said testing PCB includes a plurality of said IC testing region and said method further includes testing a plurality of pairs of solder balls and solder bumps associated with each of said IC packages.

16. The method of claim 11, wherein said testing PCB includes an electrical pin connector mounted to a surface of said testing PCB and electrically connectable to pre-determined regions of said IC die region, and testing includes determining a reliability of at least one of said pair of said solder balls and solder bumps that is electrically connectable to said electrical pin connector.

17. An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit, comprising:

a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon, vias extending through said testing PCB from a surface to an underside thereof within said IC test region, each via having an IO pad or ground pad electrically connectable thereto;

an IC package having an IC die connected thereto by solder bumps and being connected to said IC test region by solder balls, such that each of said IO pads is electrically connectable to a respective pair of said solder balls and solder bumps by said vias.

18. The apparatus of claim 17, wherein said testing PCB further includes an electrical pin connector mounted to a surface thereof and electrically connectable to pre-determined IO pads within said IC die region.

19. The apparatus of claim 17, wherein said testing PCB includes a plurality of said IC test regions.

20. The apparatus of claim 19, wherein each IC test region has an electrical pin connector electrically respectively connected to predetermined IO pads within each of said IC test regions.