EFFICIENT POWER TRANSFER POWER AMPLIFIER (PA) ARCHITECTURE

• US 20140111275A1
• Filed: 10/17/2013
• Published: 04/24/2014
• Est. Priority Date: 10/19/2012
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Khlat, Nadim, Hietala, Alexander Wayne
• Granted Patent: US 9,071,210 B2
• Time in Patent Office: Days
• US Class Current: 330/124.R
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/537 A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 3/20 Power amplifiers, e.g. Class B amplifiers, Class C amplifiers H03F3/26 - H03F3/30 take precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

An efficient power transfer power amplifier (PA) architecture is disclosed that includes a first PA, a first impedance transformation network (ITN) coupled to the first PA, a second PA, and a second ITN coupled to the second PA. A switching network having a plurality of load outputs along with a first switch input coupled to a first impedance output of the first ITN and a second switch input coupled to a second impedance output of the first ITN, a third switch input coupled to a third impedance output of the second ITN, and a fourth switch input coupled to a fourth impedance output of the second ITN. A control system is adapted to control the switching network to switch signals at the first, second, third, and fourth switch inputs such that select ones of the signals travel paths having matching impedances to loads coupled to the plurality of load outputs.

Claims

1. An efficient power transfer power amplifier (PA) architecture comprising:

a first PA;

a first impedance transformation network (ITN) having an input coupled to an output of the first PA;

a second PA;

a second ITN having an input coupled to an output of the second PA;

a switching network comprising;

a plurality of load outputs;

a first switch input coupled to a first impedance output of the first ITN;

a second switch input coupled to a second impedance output of the first ITN;

a third switch input coupled to a third impedance output of the second ITN; and

a fourth switch input coupled to a fourth impedance output of the second ITN; and

a control system adapted to control the switching network in response to a selected mode to switch signals arriving at the first switch input, the second switch input, the third switch input, and the fourth switch input such that select ones of the signals travel paths having matching impedances to loads coupled to select ones of the plurality of load outputs.

2. The efficient power transfer PA architecture of claim 1 wherein the switching network couples outputs from the first ITN and the second ITN together so that outputs of the first PA and the second PA are connected in parallel during a non-carrier aggregation (non-CA) mode.

3. The efficient power transfer PA architecture of claim 1 wherein the switching network couples outputs from the first ITN and the second ITN together so that outputs of the first PA and the second PA are not connected in parallel in order to drive separate loads during an uplink (UL) CA intra-band contiguous mode.

4. The efficient power transfer PA architecture of claim 1 further including a first power supply to power the first PA and a second power supply to power the second PA.

5. The efficient power transfer PA architecture of claim 1 wherein the first power supply outputs power to the first PA via the first ITN, and the second power supply outputs power to the second PA via the second ITN.

6. The efficient power transfer PA architecture of claim 4 wherein the first power supply and the second power supply are each a fast switched-mode power supply (Fast SMPS) type used in envelope tracking systems (ETS).

7. The efficient power transfer PA architecture of claim 4 wherein the first power supply and the second power supply are each an average power tracking (APT) type power supply that change DC supply levels during each power control slot time for long term evolution (LTE) signals.

8. The efficient power transfer PA architecture of claim 4 wherein during a non-CA UL mode output power is reduced by 3 dB from a maximum output power by deactivating either the first PA and the first power supply or the second PA and the second power supply.

9. The efficient power transfer PA architecture of claim 4 wherein the first power supply and the second power supply equally share delivering a total power and are each half the size of a single power supply for delivering an equal amount of total power.

10. The efficient power transfer PA architecture of claim 9 wherein the first PA and the second PA are each half the size of a single PA for delivering the same amount of power as a combined output of the first PA and the second PA.

11. The efficient power transfer PA architecture of claim 10 wherein the switching network includes switches that are each rated to switch half of a total power and each are half the size of switches through which the total power is deliverable.

12. The efficient power transfer PA architecture of claim 1 wherein the first ITN and the second ITN each comprise a transformerless network configured from inductors and capacitors.

13. The efficient power transfer PA architecture of claim 1 wherein the first ITN and the second ITN each comprise a tapped transformer.

14. The efficient power transfer PA architecture of claim 1 wherein the first ITN and the second ITN each comprise a dual secondary transformer.

15. An efficient power transfer power amplifier (PA) architecture comprising:

a first PA;

a first programmable impedance transformation network (PITN) having an input coupled to an output of the first PA;

a second PA;

a second PITN having an input coupled to an output of the second PA;

a switching network comprising;

a plurality of load outputs;

a first switch input coupled to an impedance output of the first PITN;

a second switch input coupled to an impedance output of the second PITN; and

a control system adapted to control the switching network in response to a selected mode to switch signals arriving at the first switch input and the second switch input to select ones of the plurality of load outputs, and to control programmable impedances of the first PITN and the second PITN such that select ones of the signals travel paths having matching impedances to loads coupled to select ones of the plurality of load outputs.

16. The efficient power transfer PA architecture of claim 15 wherein the switching network couples outputs from the first PITN and the second PITN together so that outputs of the first PA and the second PA are connected in parallel during a non-carrier aggregation (non-CA) mode.

17. The efficient power transfer PA architecture of claim 15 wherein the switching network couples outputs from the first PITN and the second PITN together so that outputs of the first PA and the second PA are not connected in parallel in order to drive separate loads during an uplink (UL) CA intra-band contiguous mode.

18. The efficient power transfer PA architecture of claim 15 further including a first power supply to power the first PA and a second power supply to power the second PA.

19. The efficient power transfer PA architecture of claim 18 wherein during a non-CA UL mode output power is reduced by 3 dB from a maximum output power by deactivating either the first PA and the first power supply or the second PA and the second power supply.

20. The efficient power transfer PA architecture of claim 18 wherein the first power supply and the second power supply equally share delivering a total power and are each half the size of a single power supply for delivering an equal amount of total power.

21. The efficient power transfer PA architecture of claim 20 wherein the first PA and the second PA are half the size of a single PA for delivering the same amount of power as a combined output of the first PA and the second PA.

22. The efficient power transfer PA architecture of claim 21 wherein the switching network includes switches that are each rated to switch half of a total power and each are half the size of switches through which the total power is deliverable.

23. The efficient power transfer PA architecture of claim 18 wherein the first power supply outputs power to the first PA via the first PITN, and the second power supply outputs power to the second PA via the second PITN.

24. The efficient power transfer PA architecture of claim 18 wherein the first power supply and the second power supply are each a fast switched-mode power supply (Fast SMPS) type used in envelope tracking systems (ETS).

25. The efficient power transfer PA architecture of claim 18 wherein the first power supply and the second power supply are each an average power tracking (APT) type power supply that change DC supply levels during each power control slot time for long term evolution (LTE) signals.

26. The efficient power transfer PA architecture of claim 15 wherein the first PITN and the second PITN each comprise a transformerless network configured from inductors and capacitors.