SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20140112049A1
• Filed: 03/14/2013
• Published: 04/24/2014
• Est. Priority Date: 10/22/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: JUNG, Sung Wook, OH, Jung Seok
• Granted Patent: US 8,854,855 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor device includes insulation patterns and cell word lines alternately stacked on a substrate. A cell channel layer is formed through the insulation patterns and the cell word lines. A select channel layer is connected to the cell channel layer, and the select channel layer has a resistance higher than a resistance of the cell channel layer. A select line surrounds the select channel layer.

Claims

1. A semiconductor memory device, comprising:

insulation patterns and cell word lines alternately stacked on a substrate;

cell channel layers formed through the insulation patterns and the cell word lines;

select channel layers connected to the cell channel layers, the select channel layers each having a resistance higher than a resistance of each of the cell channel layers; and

select lines surrounding the select channel layers.

2. The semiconductor memory device of claim 1, further comprising:

cell channel holes formed through the insulation patterns and the cell word lines, wherein the cell channel layers are formed in the cell channel holes, respectively.

3. The semiconductor memory device of claim 1, further comprising:

an insulation layer formed in each of the select channel layers.

4. The semiconductor memory device of claim 1, wherein the select channel layers comprise:

a first select channel layer connected to a lower portion of each of the cell channel layers; and

a second select channel layer connected to an upper portion of each of the cell channel layers.

5. The semiconductor memory device of claim 1, further comprising

a pipe channel layer connecting a pair of the cell channel layers.

6. The semiconductor memory device of claim 1, further comprising:

dummy word lines formed between the cell word lines and select lines closest to the cell word lines.

7. The semiconductor memory device of claim 6, wherein each of the select channel layers extends through a corresponding dummy word line.

8. A method of manufacturing a semiconductor memory device, the method comprising:

forming a first stacked structure by alternately stacking a plurality of first material layers and second material layers on a substrate;

forming cell channel layers passing through the first stacked structure; and

forming select channel layers to connected to the cell channel layers, wherein each of the select channel layers has a resistance that is greater than a resistance of the cell channel layer.

9. The method of claim 8, wherein the forming the cell channel layers comprises:

forming cell channel holes through the first stacked structure; and

forming a silicon layer in each of the cell channel holes.

10. The method of claim 9, further comprising:

forming a second stacked structure by stacking at least one third material layer and at least one fourth material layer on the first stacked structure after the forming of the cell channel layers.

11. The method of claim 10, wherein the forming the select channel layers comprises:

forming channel holes through the second stacked structure;

forming a silicon layer along a sidewall of each of the channel holes; and

forming an insulation layer on the silicon layer.

12. The method of claim 8, further comprising:

forming a second stacked structure by stacking at least one third material layer and at least one fourth material layer on the first stacked structure before the forming of the cell channel layers.

13. The method of claim 12, wherein the forming the cell channel layers comprises:

forming channel holes through the first stacked structure and through the second stacked structure;

forming a first silicon layer in each of the channel holes; and

forming a recess region by etching the first silicon layer to a boundary of the first stacked structure and the second stacked structure.

14. The method of claim 13, wherein the forming the select channel layers comprises:

forming a second silicon layer along a sidewall of the recess region; and

forming an insulation layer on the second silicon layer.

15. The method of claim 8, further comprising:

forming a third stacked structure by stacking at least one fifth material layer and at least one sixth material layer on the substrate before the forming of the first stacked structure.

16. The method of claim 15, wherein the forming the select channel layers comprises:

forming channel holes through the third stacked structure;

forming a silicon layer along a sidewall of each of the channel holes; and

forming an insulation layer on the silicon layer.

17. The method of claim 16, further comprising:

crystallizing the silicon layer.

18. The method of claim 8, further comprising:

forming a pipe gate on the substrate before the forming of the first stacked structure;

forming a pipe trench by etching the pipe gate; and

forming a pipe sacrificial layer in the pipe trench.

19. The method of claim 18, further comprising:

forming channel holes through the first stacked structure to expose the pipe sacrificial layer before the forming of cell channel layers

exposing the pipe trench by removing the pipe sacrificial layer; and

forming a pipe channel layer in the pipe trench.

20. The method of claim 19, further comprising:

crystallizing at least one of the cell channel layers, the select channel layers, or the pipe channel layer.