REFRESH METHOD, REFRESH ADDRESS GENERATOR, VOLATILE MEMORY DEVICE INCLUDING THE SAME

• US 20140112086A1
• Filed: 10/18/2013
• Published: 04/24/2014
• Est. Priority Date: 10/19/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Chul-Woo, HWANG, Hong-Sun, CHOI, Joo-Sun
• Granted Patent: US 9,042,194 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.

Claims

1. A refresh method for a volatile memory device including a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns, each row corresponding to a respective address, the refresh method comprising:

refreshing memory cells of a first set of rows of the array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and

refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period,

wherein the second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.

2. The method of claim 1, wherein the first refresh period is two times the length of the second refresh period.

3. The method of claim 1, wherein the third refresh period is one half the length of the second refresh period.

4. The method of claim 1, wherein refreshing the memory cells of the first set of rows is performed using a counter-based refresh;

and

refreshing the memory cells of the second set of rows is performed using a table-based refresh.

6. The method of claim 4, wherein the table-based refresh includes outputting a second refresh address stored in a table.

7. The method of claim 6, wherein the first refresh addresses are not stored in the table.

8. The method of claim 4, wherein the counter-based refresh is interleaved with the table-based refresh.

9. The method of claim 1, further comprising:

refreshing memory cells of a third set of rows of the array at a fourth refresh rate having a fourth refresh period, the fourth refresh rate being a higher rate having a shorter refresh period than the third refresh rate having the third refresh period, wherein at least one memory cell of each row of the fourth set of rows has a retention time longer than the fourth refresh period and shorter than the third refresh period.

10. The method of claim 1, wherein refresh intervals between refreshing the rows of the array are the same as refresh intervals used in the standard for the volatile memory device.

5. The method of 4, wherein the counter-based refresh includes generating a refresh address at each increase of a counter value.

11. A refresh method for a volatile memory device including a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns, each row corresponding to a respective address, the refresh method comprising:

refreshing memory cells of a first set of rows of the array at a first refresh rate having a first refresh period, based on a counter-based refresh, wherein the memory cells of the first set of rows have a retention time longer than the first refresh period; and

refreshing memory cells of a second set of rows of the array at a second refresh rate having a second refresh period, based on a table-based refresh, the second refresh rate being a higher rate having a shorter refresh period than the first refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the second refresh period and shorter than the first refresh period.

12. The refresh method of claim 11, wherein the first refresh period is longer than a refresh period defined in a standard for the volatile device.

13. The refresh method of claim 11, further comprising refreshing memory cells of a third set of rows of the array at a third refresh rate having a third refresh period, based on a table-based refresh, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the third set of rows has a retention time longer than the third refresh period and shorter than the second refresh period.

15. The method of claim 11, wherein the table-based refresh includes outputting a refresh address stored in a table.

16. The method of claim 11, wherein refreshing the memory cells of the first set of rows of the memory array is interleaved with refreshing the memory cells of the second set of rows of the memory array.

14. The method of 11, wherein the counter-based refresh includes generating a first refresh address at each increase of a counter value.

17. A method of performing a refresh operation in a memory device including a memory array having rows and columns, comprising:

performing a first refresh sub-operation by cycling through all of the rows of the memory array consecutively at equally spaced first time intervals based on a counter, such that each row of the first refresh sub-operation is refreshed subsequent to an adjacent previously refreshed row of the first refresh sub-operation after an occurrence of the first time interval, wherein the time between two refreshes of the same row in the first refresh sub-operation is referred to as a refresh cycle; and

performing a second refresh sub-operation within the refresh cycle on a plurality of first rows of the memory array based on information stored in a table, and not performing the second refresh sub-operation within the refresh cycle on a plurality of second rows of the memory array,

wherein the plurality of first rows each include at least one cell that has a first retention time, and

wherein the plurality of second rows include a plurality of cells that have retention times longer than the first retention time.

18. The method of claim 17, wherein the first refresh sub-operation is interleaved with the second refresh sub-operation.

19. The method of claim 17, wherein the first refresh sub-operation is performed using time intervals greater than an industry standard for the memory device.

20. The method of claim 19, wherein the second sub-operation includes refreshing certain rows of the memory array at time intervals less than the industry standard for the memory device.