Hybrid Timing Recovery for Burst Mode Receiver in Passive Optical Networks

• US 20140112356A1
• Filed: 10/23/2012
• Published: 04/24/2014
• Est. Priority Date: 10/23/2012
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Cheng, Ning
• Granted Patent: US 9,106,400 B2
• Time in Patent Office: Days
• US Class Current: 370/517
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0335 Gardner detector

Abstract

An apparatus for coarse phase alignment of an analog signal comprising: a tapped delay line, a coarse phase alignment logic circuit coupled to the tapped delay line, and a selector coupled to the tapped delay and the coarse phase alignment logic circuit. An apparatus for timing and data recovery for burst mode receivers comprising: a receiver, a coarse phase alignment circuit coupled to the receiver, at least one analog to digital converter (ADC) coupled to the coarse phase alignment circuit such that the coarse phase alignment circuit is positioned between the receiver and the ADC, and a fine phase alignment circuit coupled to the ADC such that the ADC is positioned between the coarse phase alignment circuit and the fine phase alignment circuit, wherein the fine phase alignment circuit produces a recovered data output.

Claims

1. An apparatus for coarse phase alignment of an analog signal comprising:

a tapped delay line;

a coarse phase alignment logic circuit coupled to the tapped delay line; and

a selector coupled to the tapped delay and the coarse phase alignment logic circuit.

2. The apparatus of claim 1 further comprising a plurality of flip-flops coupled to the tapped delay line such that the flip-flops are positioned between the tapped delay line and the coarse phase alignment logic circuit, and wherein the coarse phase alignment circuit is positioned between the flip-flops and the selector.

3. The apparatus of claim 2, wherein from 2 to 16 flip-flops are positioned between the tapped delay line and the coarse phase alignment logic.

4. The apparatus of claim 3, wherein four flip-flops are positioned between the tapped delay line and the coarse phase alignment logic.

5. The apparatus of claim 1, wherein the tapped delay line is coupled to an optical receiver.

6. The apparatus of claim 1, wherein the tapped delay line is coupled to a clock.

7. An apparatus for timing and data recovery for burst mode receivers comprising:

a receiver;

a coarse phase alignment circuit coupled to the receiver, wherein the coarse phase alignment circuit comprises a tapped delay line;

at least one analog to digital converter (ADC) coupled to the coarse phase alignment circuit such that the coarse phase alignment circuit is positioned between the receiver and the ADC; and

a fine phase alignment circuit coupled to the ADC such that the ADC is positioned between the coarse phase alignment circuit and the fine phase alignment circuit, wherein the fine phase alignment circuit produces a recovered data output.

8. The apparatus of claim 7, wherein the coarse phase alignment circuit comprises:

a plurality of flip-flops coupled to the tapped delay line such that the tapped delay line is positioned between a clock and the flip-flops, wherein the flip-flops are further coupled to the receiver;

a coarse phase alignment logic circuit coupled to the flip-flops such that the flip-flops are positioned between the tapped delay line and the coarse phase alignment logic circuit; and

a selector directly connected to the tapped delay line and coupled to the coarse phase alignment logic circuit, wherein the coarse phase alignment logic circuit is positioned between the flip-flops and the selector, wherein the tapped delay line is positioned between the clock and the selector, and wherein the selector is further coupled to the ADC.

9. The apparatus of claim 7, wherein the coarse phase alignment circuit comprises:

a tapped delay line;

a plurality of flip-flops coupled to the tapped delay line such that the tapped delay line is positioned between the receiver and the flip-flops, wherein the flip-flops are further coupled to a clock;

a coarse phase alignment logic circuit coupled to the flip-flops such that the flip-flops are positioned between the tapped delay line and the coarse phase alignment logic circuit; and

a selector directly connected to the tapped delay line and coupled to the coarse phase alignment logic circuit, wherein the coarse phase alignment logic circuit is positioned between the flip-flops and the selector, wherein the tapped delay line is positioned between the receiver and the selector, and wherein the selector is further coupled to the ADC.

10. The apparatus of claim 9, wherein the fine phase alignment circuit comprises:

an interpolator coupled to the ADC such that the ADC is positioned between the coarse phase alignment circuit and the interpolator;

a timing error estimator coupled to the interpolator such that the interpolator is positioned between the timing error estimator and the ADC; and

a loop filter coupled to the interpolator and the timing error estimator such the loop filter is positioned between the interpolator and the timing error estimator.

11. The apparatus of claim 10 further comprising a comparator coupled to the interpolator such that the interpolator is positioned between the comparator and the ADC, wherein the timing error estimator is positioned between the comparator and the loop filter.

12. The apparatus of claim 9, wherein the tapped delay line has from 2 to 16 taps.

13. The apparatus of claim 9, wherein the fine phase alignment circuit comprises:

a phase shifter coupled to the clock and to the ADC, wherein the phase shifter is positioned between the clock and the ADC, and wherein the phase shifter is not directly connected to the coarse phase alignment circuit; and

a timing error estimator coupled to the phase shifter and the ADC.

14. The apparatus of claim 13 further comprising a comparator coupled to the ADC and the timing error estimator, wherein the ADC is positioned between the comparator and the selector, and wherein the timing error estimator is positioned between the comparator and the phase shifter.

15. The apparatus of claim 14, wherein the fine phase alignment circuit is configured to use a Mueller-Muller algorithm or a Gardner algorithm for timing error estimation.

16. A method of burst mode clock and data recovery at an Optical Line Terminal (OLT) in a Passive Optical Network (PON) comprising the steps of:

receiving an upstream analog signal;

aligning a coarse phase for the upstream analog signal using a fractional delay circuit;

converting the coarse phase aligned upstream analog signal to a digital signal;

aligning a fine phase for the digital signal; and

outputting a recovered data signal.

17. The method of claim 16, wherein aligning the coarse phase comprises:

comparing fractionally delayed versions of the upstream analog signal to a system clock; and

selecting a single fractionally delayed version of the upstream signal for usage in data recovery.

18. The method of claim 16, wherein aligning the coarse phase comprises:

comparing fractionally delayed version of a system clock to the upstream analog signal; and

selecting a single fractionally delayed version of the system clock signal for usage in data recovery.

19. The method of claim 16, wherein converting is accomplished by at least one analog to digital converter running at the nominal bit rate.

20. The method of claim 16, wherein the method is accomplished in less than a 44 bit period.