GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL

• US 20140115219A1
• Filed: 12/30/2013
• Published: 04/24/2014
• Est. Priority Date: 08/24/2001
• Status: Active Grant

• Current Assignee: Blaise fanning, David Harriman, David Lee, Jasmin Ajanovic
• Original Assignee: Blaise fanning, David Harriman, David Lee, Jasmin Ajanovic
• Inventors: Ajanovic, Jasmin, Harriman, David, Fanning, Blaise, Lee, David
• Granted Patent: US 9,836,424 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: A47K 7/028 having a rigid handle A47K7/026 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4273 using a clocked protocol
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

An enhanced general input/output communication architecture, protocol and related methods are presented.

Claims

1. An apparatus, comprising:

a protocol stack including layers to communicate data over an interconnect;

wherein the protocol stack including layers comprises a data link layer, and a transactions layer;

a transmitter having a first register and a second register;

wherein the transmitter is to transmit data on a point to point interconnect;

wherein the first register is to store a number of credits received and the second register is to store a number of credits used; and

a receiver having at least one register;

wherein the at least one register of the receiver is to hold a value to represent a total number of credits sent.

2. The apparatus of claim 1, wherein the first register is to receive the number of credits received from a remote receiver.

3. The apparatus of claim 1, wherein the transmitter is to determine when a remote receiver is temporarily unable to receive more content according to the number of credits received stored in the first register.

4. The apparatus of claim 1, wherein the first register, second register, and the at least one register of the receiver has a storage capacity of 8 bits.

5. The apparatus of claim 1, wherein the first register, second register, and the at least one register of the receiver are to store the number of credits received, the number of credits used, and the number of credits sent, respectively, modulo 256.

6. The apparatus of 1, wherein the number of credits received to be stored in the first register of the transmitter is sent to the transmitter in form of a message.

7. The apparatus of claim 6, wherein number of credits sent in the at least one register is set to a maximum payload size of the register upon reset or power-up.

8. The apparatus of claim 6, wherein the numbers of credits received in the first register and the second register are set to zero upon reset or power-up.

9. A method, comprising:

utilizing a protocol stack including layers to communicate data over an interconnect;

wherein the protocol stack including layers comprises a data link layer, and a transactions layer;

utilizing a transmitter having a first register to store a number of credits received and a second register to store a total number of credits used; and

utilizing the transmitter to transmit data on a point to point interconnect; and

utilizing a receiver having at least one register to hold a value to represent a total number of credits sent.

10. The method of claim 9 further comprising utilizing a remote receiver to transmit information about a current memory space availability to store data in the transmitter.

11. The method of claim 9, wherein at least one message having the number of credits received and the number of credits used which are to be stored in the first and second registers are sent from a remote device to the transmitter.

12. The method of claim 11, wherein the at least one message is to achieve flow control of data between two unique apparati.

13. The method of claim 9 further comprising resetting the number of credits received and credits used in the first and second registers to zero upon power-up or reset.

14. The method of claim 9 further comprising refraining from sending packets from a transmitter to a remote receiver when the value in the first register is equal to zero.

15. The method of claim 14, wherein the receiver is to send a number of credits received and a number of credits used to a transmitter in a remote device.

16. The method of claim 14 further comprising utilizing the first register to control the speed of data transfer from the transmitter to a receiver in a remote device.

17. A non-transitory computer readable medium storing computer readable instructions for machine execution of a method for:

a protocol stack including layers to communicate data over an interconnect;

wherein the protocol stack including layers comprises a data link layer, and a transactions layer;

a transmitter having a first register and a second register;

wherein the first register is to store a number of credits received and the second register is to store a total number of credits used;

wherein the transmitter is to transmit data on a point to point interconnect; and

a receiver having at least one register;

wherein the at least one register of the receiver is to hold a value to represent a total number of credits sent.

18. The non-transitory computer readable medium of claim 17, wherein at least one message which includes the number of credits available is communicated from a first device to a second device.

19. The non-transitory computer readable medium of claim 17, wherein the at least one register of the receiver is to store a total number of credits sent.

20. A system-on-a-chip (SoC) embedded within a mobile device, comprising:

a protocol stack including layers to communicate data over an interconnect;

wherein the protocol stack including layers comprises a data link layer, and a transactions layer;

a transmitter having a first register and a second register;

wherein the transmitter is to transmit data on a point to point interconnect;

wherein the first register is to store a number of credits received and the second register is to store a total number of credits used;

a receiver having at least one register; and

wherein the at least one register of the receiver is to store a total number of credits sent.

21. The SoC of claim 20 is an embedded component within a cellular phone.