DATA PROCESSING SYSTEM WITH DATA CHARACTERISTIC BASED IDENTIFICATION OF CORRESPONDING INSTRUCTIONS

• US 20140115300A1
• Filed: 10/23/2012
• Published: 04/24/2014
• Est. Priority Date: 10/23/2012
• Status: Active Grant

• Current Assignee: CA, Inc. (d/b/a CA Technologies) (Broadcom, Inc.)
• Original Assignee: CA, Inc. (d/b/a CA Technologies) (Broadcom, Inc.)
• Inventors: Bodine, Gregory Lewis
• Granted Patent: US 9,632,787 B2
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: H04L 43/0876 Network utilisation, e.g. volume of load or congestion level
• CPC Class Codes: H04L 63/10 for controlling access to devices or network resources

Abstract

Some methods, computer program products, and data processing nodes identify a data unit in a data memory that is to be operated upon by a processor circuit, and uses a characteristic of the data unit to identify what instruction(s) within an instruction memory is be executed by the processor circuit to perform an operation upon the data unit. The data memory may be local to the processor circuit, and the instruction memory may be remotely accessible to the processor circuit through a data network.

Claims

1. A method comprising:

selecting a data unit, from among a plurality of data units in a data memory, that is to be operated upon by a processor circuit;

identifying an instruction, among a plurality of instructions in an instruction memory, responsive to a characteristic of the data unit; and

requesting the instruction from the instruction memory for execution by the processor circuit to operate on the data unit.

2. The method of claim 1, further comprising:

receiving the instruction from the instruction memory; and

executing the instruction by the processor circuit to perform a defined operation on the data unit.

3. The method of claim 1, wherein identifying the instruction, among the plurality of instructions in the instruction memory, responsive to the characteristic of the data unit, comprises:

receiving the data unit from the data memory;

examining content of the data unit to identify an address to the instruction within the instruction memory; and

retrieving the instruction from the address within the instruction memory.

4. The method of claim 3, wherein:

examining content of the data unit to identify the address to the instruction within the instruction memory comprises identifying a network address for accessing the instruction memory of an instruction storage node through a data network; and

retrieving the instruction from the address within the instruction memory comprises communicating a message through the data network that is directed to the network address and requests retrieval of the instruction from the instruction memory of the instruction storage node.

5. The method of claim 4, wherein:

identifying the network address for accessing the instruction memory of the instruction storage node through the data network comprises identifying a Uniform Resource Locator (URL) address from the content of the data unit, the URL address identifying a location of a network accessible file containing the instruction; and

communicating the message through the data network that is directed to the network address and requests retrieval of the instruction comprises communicating a file read request message that identifies the URL address.

6. The method of claim 3, wherein examining content of the data unit to identify the address to the instruction within the instruction memory, comprises:

determining the address to the instruction responsive to a plurality of defined bit locations of the data unit; and

determining a data content portion of the data unit that is to be operated upon by the instruction responsive to other defined bit locations of the data unit.

7. The method of claim 3, wherein examining content of the data unit to identify an address to the instruction within the instruction memory, comprises:

determining a location within a configuration file responsive to the content of the data unit;

obtaining information from the location within the configuration file; and

identifying the address to the instruction in response to the information.

8. The method of claim 3, wherein:

a plurality of configuration files are associated with different groups of the plurality of instructions in the instruction memory; and

examining content of the data unit to identify the address to the instruction within the instruction memory comprises;

selecting one of the plurality of configuration files responsive to the content of the data unit; and

identifying the address to the instruction in response to information contained in the one of the plurality of configuration files that was selected.

9. The method of claim 1, wherein identifying the instruction, among the plurality of instructions in an instruction memory, responsive to the characteristic of the data unit, comprises:

determining one of a plurality of defined execution cycle rates at which the instruction will be scheduled for execution by the processor circuit, responsive to the characteristic of the data unit; and

identifying the address to the instruction in response to the one of the plurality of defined execution cycle rates.

10. The method of claim 1, wherein identifying the instruction, among the plurality of instructions in an instruction memory, responsive to the characteristic of the data unit, comprises:

determining one of a plurality of defined execution priority levels at which the instruction will be prioritized for execution by the processor circuit, responsive to the characteristic of the data unit; and

identifying the address to the instruction in response to the one of the plurality of defined execution priority levels.

11. The method of claim 1, further comprising:

receiving the data unit and a pointer to the instruction in the instruction memory through an application programming interface.

12. A computer program product comprising:

a computer readable storage medium having computer readable program code embodied therein, the computer readable program code comprising;

computer readable program code configured to select a data unit, from among a plurality of data units in a data memory, that is to be operated upon by a processor circuit;

computer readable program code configured to identify an instruction, among a plurality of instructions in an instruction memory, responsive to a characteristic of the data unit;

computer readable program code configured to request the instruction from the instruction memory for execution by the processor circuit to operate on the data unit.

13. The computer program product of claim 12, wherein the computer readable program code configured to identify the instruction, among the plurality of instructions in the instruction memory, responsive to the characteristic of the data unit, comprises:

computer readable program code configured to receive the data unit from the data memory;

computer readable program code configured to examine content of the data unit to identify an address to the instruction within the instruction memory; and

computer readable program code configured to retrieve the instruction from the address within the instruction memory.

14. The computer program product of claim 13, wherein:

the computer readable program code configured to examine content of the data unit to identify the address to the instruction within the instruction memory comprises computer readable program code configured to identify a network address for accessing the instruction memory of an instruction storage node through a data network; and

the computer readable program code configured to retrieve the instruction from the address within the data unit comprises computer readable program code configured to communicate a message through the data network that is directed to the network address and requests retrieval of the instruction from the instruction memory of the instruction storage node.

15. The computer program product of claim 13, wherein the computer readable program code configured to examine content of the data unit to identify the address to the instruction within the instruction memory, comprises:

computer readable program code configured to determine the address to the instruction responsive to a plurality of defined bit locations of the data unit; and

computer readable program code configured to determine a data content portion of the data unit that is to be operated upon by the instruction responsive to other defined bit locations of the data unit.

16. The computer program product of claim 13, wherein the computer readable program code configured to examine content of the data unit to identify the address to the instruction within the instruction memory, comprises:

computer readable program code configured to determine a location within a configuration file responsive to the content of the data unit;

computer readable program code configured to obtain information from the location within the configuration file; and

computer readable program code configured to identify the address to the instruction in response to the information.

17. The computer program product of claim 13, wherein:

a plurality of configuration files are associated with different groups of the plurality of instructions in the instruction memory; and

the computer readable program code configured to examine content of the data unit to identify the address to the instruction within the instruction memory comprises;

computer readable program code configured to select one of the plurality of configuration files responsive to the content of the data unit; and

computer readable program code configured to identify the address to the instruction in response to information contained in the one of the plurality of configuration files that was selected.

18. The computer program product of claim 12, wherein the computer readable program code configured to identify the instruction, among the plurality of instructions in an instruction memory, responsive to the characteristic of the data unit, comprises:

computer readable program code configured to select one of a plurality of defined execution cycle rates at which the instruction will be scheduled for execution by the processor circuit, responsive to the characteristic of the data unit; and

computer readable program code configured to identify the address to the instruction in response to the one of the plurality of defined execution cycle rates.

19. The computer program product of claim 12, wherein the computer readable program code configured to identify the instruction, among the plurality of instructions in an instruction memory, responsive to the characteristic of the data unit, comprises:

computer readable program code configured to select one of a plurality of defined execution priority levels at which the instruction will be prioritized for execution by the processor circuit, responsive to the characteristic of the data unit; and

computer readable program code configured to identify the address to the instruction in response to the one of the plurality of defined execution priority levels.

20. The computer program product of claim 12, further comprising:

computer readable program code configured to receive the data unit and a pointer to the instruction in the instruction memory through an application programming interface.

21. A data processing node comprising:

a network interface to communicate through a data network with an instruction memory;

a data memory comprising a plurality of data units; and

a processor circuit to select a data unit from among the plurality of data units in the data memory, to identify an instruction, among a plurality of instructions in the instruction memory, responsive to a characteristic of the data unit, and to request the instruction from the instruction memory for execution by the processor circuit to operate on the data unit.

22. The data processing node of claim 21, wherein:

the processor circuit is further to receive the data unit from the data memory through the network interface, to identify a Uniform Resource Locator (URL) address from the content of the data unit that identifies a location of a network accessible file in the instruction memory containing the instruction, and to communicate a file read request message that identifies the URL address through the network interface.

23. The data processing node of claim 21, wherein:

the processor circuit is further to determine an address to the instruction within the instruction memory responsive to a plurality of defined bit locations of the data unit, and to determine a data content portion of the data unit that is to be operated upon by the instruction responsive to other defined bit locations of the data unit.

24. The data processing node of claim 21, wherein:

the processor circuit is further to determine a location within a configuration file responsive to the content of the data unit, to obtain information from the location within the configuration file, and to identify an address to the instruction within the instruction memory in response to the information.

25. The data processing node of claim 21, wherein:

the processor circuit is further to select one of a plurality of defined execution cycle rates at which the instruction will be scheduled for execution by the processor circuit, responsive to the characteristic of the data unit, and to identify an address to the instruction within the instruction memory in response to the one of the plurality of defined execution cycle rates.

26. The data processing node of claim 21, wherein:

the processor circuit is further to select one of a plurality of defined execution priority levels at which the instruction will be prioritized for execution by the processor circuit, responsive to the characteristic of the data unit, and to identify an address to the instruction within the instruction memory in response to the one of the plurality of defined execution priority levels.