MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM USING RECONSTRUCTED DATA

• US 20140115424A1
• Filed: 10/14/2013
• Published: 04/24/2014
• Est. Priority Date: 10/22/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KONG, Jun-Jin, SON, Hong-Rak, YOO, Hyun-Seuk, SEOL, Chang-Kyu, YOO, Young-Geon
• Granted Patent: US 9,098,391 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

Provided is a method of operating a memory system. The method includes programming first bit data into multiple memory cells; identifying target memory cells that are in a first state and have threshold voltages equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating multiple third bit data by performing a first process on the second bit data; and selecting third bit data of the calculated multiple third bit data that changes a largest number of target memory cells from the first state to a second state when the memory cells are programmed with each of the multiple third bit data, respectively. The selected third bit data is programmed into the memory cells.

Claims

1. A method of operating a memory system, the method comprising:

programming first bit data into a plurality of memory cells;

identifying target memory cells that are in a first state and have threshold voltages equal to or greater than a first voltage from the plurality of memory cells programmed with the first bit data;

receiving second bit data which is to be programmed into the plurality of memory cells;

calculating a plurality of third bit data by performing a first process on the second bit data;

selecting third bit data of the calculated plurality of third bit data that changes a largest number of target memory cells from the first state to a second state when the memory cells are programmed with each of the plurality of third bit data, respectively; and

programming the selected third bit data into the memory cells.

2. The method of claim 1, wherein the second bit data is most significant bit (MSB) data.

3. The method of claim 1, wherein the first state is an erase state.

4. The method of claim 1, wherein calculating of the plurality of third bit data by performing the first process on the second bit data comprises performing a first operation on the second bit data with a plurality of predetermined masks.

5. The method of claim 4, further comprising:

programming an address of a mask used to calculate the selected third bit data into the memory cells.

6. The method of claim 5, wherein each of the memory cells comprises a data area and a spare area, and

wherein programming the selected third bit data into the memory cells comprises programming the selected third bit data into the data area, and programming the address of the mask used to calculate the selected third bit data into the memory cells comprises programming the address of the mask used to calculate the selected third bit data into the spare area.

7. The method of claim 4, further comprising:

reading the selected third bit data after programming the selected third bit data into the memory cells;

reconstructing the second bit data by performing a second process on the read third bit data; and

outputting the reconstructed second bit data.

8. The method of claim 7, wherein performing the second process comprises performing a second operation on the read third bit data with the mask used to calculate the selected third bit data.

9. The method of claim 8, wherein the first operation and the second operation are XOR operations.

10. The method of claim 7, further comprising:

performing error correcting code (ECC) encoding on the selected third bit data before the selected third bit data is programmed into the memory cells; and

performing ECC decoding on the programmed third bit data before reading the selected third bit data.

11. The method of claim 1, wherein identifying of the target memory cells comprises splitting the first bit data into n first data segments and identifying target memory cells which are in the first state and have threshold voltages equal to or greater than the first voltage from the memory cells programmed with the first data segments,

wherein calculating of the plurality of third bit data comprises splitting the second bit data into n second data segments and calculating a plurality of third data segments by performing a third process on the second data segments, and

wherein selecting the third bit data comprises selecting a third data segment which changes the largest number of target memory cells from the first state to the second state when the memory cells are programmed with each of the third data segments from the third data segments, selecting the selected third data segment for each of the n second data segments, and combining the n selected third data segments into third bit data, wherein n is a natural number.

12. A memory system, comprising:

a nonvolatile memory device comprising a plurality of memory cells;

an input/output (I/O) device configured to receive first bit data and second bit data which are to be programmed into the memory cells; and

a controller configured to control the nonvolatile memory device,

wherein the nonvolatile memory device comprises control logic configured to identify target memory cells from the memory cells programmed with the first bit data, the target memory cells being in a first state and having threshold voltages equal to or greater than a first voltage, and

wherein the controller comprises;

a read-only memory (ROM) configured to store a plurality of masks;

a microprocessor configured to calculate a plurality of third bit data by performing a first operation on the second bit data with the plurality of masks, respectively;

a random-access memory (RAM) configured to store the plurality of third bit data calculated by the microprocessor; and

a counter configured to count the number of target memory cells which change from the first state to a second state when the memory cells are programmed with each of the plurality of third bit data, and to provide the counting results to the microprocessor, the microprocessor being further configured to select third bit data of the plurality of third bit data which produces a largest counting result, and to program the selected third bit data into the nonvolatile memory device.

13. The memory system of claim 12, wherein the nonvolatile memory device is configured to store an address of a mask used to calculate the selected third bit data.

14. The memory system of claim 13, wherein the microprocessor is further configured to reconstruct the second bit data by performing a second operation on the programmed third bit data with the mask used to calculate the selected third bit data, and

wherein the I/O device is further configured to output the reconstructed second bit data.

15. The memory system of claim 12, wherein the masks stored in the ROM have different bit patterns.

16. A method of operating a memory system, the method comprising:

programming first bit data into a plurality of memory cells;

splitting the first bit data into a plurality of first data segments;

identifying target memory cells that are in a first state and have threshold voltages equal to or greater than a first voltage from the plurality of memory cells programmed with the first data segments;

receiving second bit data which is to be programmed into the plurality of memory cells;

splitting the second bit data into a plurality of second data segments;

calculating a plurality of third data segments for each of the plurality of second data segments by performing a first process on the corresponding second data segment;

selecting a third data segment of the plurality of third data segments that changes a largest number of target memory cells from the first state to a second state within each of the plurality of second data segments, respectively, to provide a plurality of selected third data segments;

combining the plurality of selected third data segments into third bit data; and

programming the third bit data into the plurality of memory cells.

17. The method of claim 16, further comprising:

reading the programmed third bit data from the plurality of memory cells;

splitting the read third bit data into the plurality of third data segments; and

reconstructing the plurality of second data segments by performing a second process on the plurality of third data segments, respectively.

18. The method of claim 17, wherein performing the first process comprises performing a first operation on the second data segment with a plurality of masks corresponding to the plurality of third data segments, and

wherein performing the second process comprises performing a second operation on the plurality of third data segments with the plurality of masks corresponding to the plurality of third data segments.

19. The method of claim 18, wherein each of the first operation and the second operation comprises an exclusive or (XOR) operation.

20. The method of claim 17, further comprising:

combining the reconstructed plurality of second data segments into reconstructed second bit data; and

outputting the reconstructed second bit data.