ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE

• US 20140117359A1
• Filed: 01/31/2013
• Published: 05/01/2014
• Est. Priority Date: 10/26/2012
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: YUAN, Guangcai, LEE, Woobong
• Application Number:
  US13/755,100
• Publication Number:
  US 20140117359A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention relate to a display device, an array substrate and a method for manufacturing the same. The array substrate includes a substrate and a thin film transistor and a pixel electrode which are formed on the substrate, the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes and is overlaid with a passivation layer, the active layer of the thin film transistor is of an oxide semiconductor, and the passivation layer comprises at least one layer of inorganic insulating thin film or organic insulating thin film. With this array substrate, the oxide semiconductor can be effectively avoided from being affected by hydrogen-containing groups, so that stability of the whole TFT device is enhanced to a great extent, and yield of final products is increased.

Claims

1. An array substrate, comprising a substrate and a thin film transistor and a pixel electrode which are formed on the substrate, the thin film transistor comprising a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes, and being overlaid with a multilayered passivation layer;

wherein the active layer of the thin film transistor is of an oxide semiconductor; and

the multilayered passivation layer comprises at least one layer of inorganic insulating thin film or organic insulating thin film.

2. The array substrate claimed as claim 1, wherein the multilayered passivation layer includes a first passivation layer, a second passivation layer, and a third passivation layer which are disposed in sequence;

wherein the first passivation layer is close to the thin film transistor;

the first passivation layer is a first inorganic insulating layer, which comprises a silicon oxide thin film, an aluminum oxide thin film, a titanium oxide thin film, a silicon oxynitride thin film, a zirconium oxide thin film, a tantalum oxide thin film, a barium titanate thin film or a neodymium oxide thin film;

the second passivation layer is a second inorganic insulating layer or a first organic insulating layer;

the second inorganic insulating layer comprises a silicon oxynitride thin film, an aluminum oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, or a neodymium oxynitride thin film; and

the first organic insulating layer comprises a resin insulating thin film or an acrylic insulating thin film; and

the third passivation layer is a third inorganic insulating layer or a second organic insulating layer;

the third inorganic insulating layer comprises a silicon nitride thin film, an aluminum nitride thin film, a zirconium nitride thin film, or a tantalum nitride thin film; and

the second organic insulating layer comprises a resin insulating thin film or an acrylic insulating thin film.

3. The array substrate claimed as claim 2, wherein the multilayered passivation layer further includes a fourth passivation layer disposed on the third passivation layer;

the first passivation layer is the first inorganic insulating layer, which comprises a silicon oxide thin film, an aluminum oxide thin film, a titanium oxide thin film, a silicon oxynitride thin film, a zirconium oxide thin film, a tantalum oxide thin film, a barium titanate thin film, a neodymium oxide thin film, an aluminum oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, or a neodymium oxynitride thin film;

the second passivation layer is the second inorganic insulating layer, which comprises an aluminum oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, or a neodymium oxynitride thin film;

the third passivation layer is the third inorganic insulating layer, which comprises a silicon nitride thin film, an aluminum nitride thin film, a zirconium nitride thin film, or a tantalum nitride thin film; and

the fourth passivation layer is a first organic insulating layer, which comprises a resin insulating thin film or an acrylic insulating thin film.

4. The array substrate claimed as claim 2, wherein a thickness of the first passivation layer is 50 nm˜

600 nm;

when the second passivation layer is an inorganic insulating layer, a thickness of the second passivation layer is 50 nm˜

650 nm; and

when the second passivation layer is an organic insulating layer, a thickness of the second passivation layer is 0.5 μ

m˜

2.5 μ

m;

when the third passivation layer is an inorganic insulating layer, a thickness of the third passivation layer is 50 nm˜

500 nm; and

when the third passivation layer is an organic insulating layer, a thickness of the third passivation layer is 0.5 μ

m˜

2.5 μ

m.

5. The array substrate claimed as claim 3, wherein the multilayered passivation layer further includes a fifth passivation layer provided on the fourth passivation layer;

the fifth passivation layer is a fourth inorganic insulating layer, which comprises a silicon oxynitride thin film, a silicon oxide thin film, a zirconium oxide thin film, a tantalum oxide thin film, a barium titanate thin film, a neodymium oxide thin film, an aluminum oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, a neodymium oxynitride thin film, a silicon nitride thin film, an aluminum nitride thin film, a zirconium nitride thin film or a tantalum nitride thin film.

6. The array substrate claimed as claim 5, wherein a thickness of the first passivation layer is 50 nm˜

600 nm;

a thickness of the second passivation layer is 50 nm˜

650 nm;

a thickness of the third passivation layer is 50 nm˜

500 nm;

a thickness of the fourth passivation layer is 0.5 μ

m˜

2.5 μ

m; and

a thickness of the fifth passivation layer is 20 nm˜

450 nm.

7. The array substrate claimed as claim 1, wherein the multilayered passivation layer includes a first passivation layer and a second passivation layer;

wherein the first passivation layer is close to the thin film transistor;

the first passivation layer is a first inorganic insulating layer, which comprises a silicon oxide thin film, an aluminum oxide thin film, an yttrium oxide thin film, a zirconium oxide thin film, a tantalum oxide thin film, a barium titanate thin film, a neodymium oxide thin film or a silicon oxynitride thin film;

the second passivation layer is a second inorganic insulating layer or a first organic insulating layer;

the second inorganic insulating layer comprises a silicon nitride thin film, an yttrium oxide thin film, a silicon oxynitride thin film, a zirconium oxide thin film, a tantalum oxide thin film, a barium titanate thin film or a neodymium oxide thin film; and

the first organic insulating layer comprises a resin insulating thin film or an acrylic insulating thin film.

8. The array substrate claimed as claim 7, wherein a thickness of the first passivation layer is 50 nm˜

600 nm;

when the second passivation layer is an inorganic insulating layer, a thickness of the second passivation layer is 50 nm˜

500 nm; and

when the second passivation layer is an organic insulating layer, a thickness of the second passivation layer is 0.5 μ

m˜

2.4 μ

m.

9. The array substrate claimed as claim 7, wherein each of the first passivation layer and the second passivation layer is a passivation layer subjected to an annealing process.

10. The array substrate claimed as claim 1, wherein the gate insulating layer is located between the active layer and the gate electrode;

and the gate insulating layer comprises at least one layer of inorganic insulating thin film.

11. The array substrate claimed as claim 10, wherein the gate insulating layer includes a first gate insulating layer close to the gate electrode and a second gate insulating layer close to the active layer;

the first gate insulating layer is an aluminum oxynitride thin film, a silicon oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, an yttrium oxynitride thin film, a neodymium oxynitride thin film, a silicon nitride thin film, an aluminum nitride thin film, a zirconium nitride thin film or a tantalum nitride thin film; and

the second gate insulating layer is a silicon oxide thin film, an yttrium oxide thin film, an aluminum oxide thin film, a titanium oxide thin film, a zirconium oxide thin film, a tantalum oxide thin film, a barium titanate thin film, a neodymium oxide thin film, an aluminum oxynitride thin film, a silicon oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, an yttrium oxynitride thin film or a neodymium oxynitride thin film.

12. The array substrate claimed as claim 11, wherein the first gate insulating layer is an insulating layer subjected to an annealing process;

and the second gate insulating layer is an insulating layer subjected to an annealing process.

13. The array substrate claimed as claim 11, wherein a thickness of the first gate insulating layer is 50 nm-600 nm;

and a thickness of the second gate insulating layer is 50 nm-650 nm.

14. The array substrate claimed as claim 10, wherein the gate insulating layer includes a first gate insulating layer close to the gate electrode, a second gate insulating layer, and a third gate insulating layer close to the active layer, and the second gate insulating layer is located between the first gate insulating layer and the third gate insulating layer;

wherein the first gate insulating layer is an aluminum oxynitride thin film, a silicon oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, an yttrium oxynitride thin film, a neodymium oxynitride thin film, a silicon nitride thin film, an aluminum nitride thin film, a zirconium nitride thin film or a tantalum nitride thin film;

the second gate insulating layer is an aluminum oxynitride thin film, a silicon oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, an yttrium oxynitride thin film, or a neodymium oxynitride thin film; and

the third gate insulating layer is a silicon oxide thin film, an yttrium oxide thin film, an aluminum oxide thin film, a titanium oxide thin film, a zirconium oxide thin film, a tantalum oxide thin film, a barium titanate thin film, a neodymium oxide thin film, an aluminum oxynitride thin film, a silicon oxynitride thin film, a zirconium oxynitride thin film, a tantalum oxynitride thin film, an yttrium oxynitride thin film or a neodymium oxynitride thin film.

15. The array substrate claimed as claim 1, wherein the gate electrode and/or the source and drain electrodes are electrodes of copper or copper alloy.