INTERLAYER DIELECTRIC FOR NON-PLANAR TRANSISTORS

• US 20140117425A1
• Filed: 12/06/2011
• Published: 05/01/2014
• Est. Priority Date: 12/06/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Pradhan, Sameer, Luce, Jeanne
• Granted Patent: US 9,087,915 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

Claims

1. A method of fabricating a microelectronic transistor, comprising:

forming a transistor gate including a gate electrode adjacent a substrate and a pair of gates spacers on opposing sides of the gate electrode;

forming a source/drain region;

forming a first interlayer dielectric material layer adjacent the source/drain region and adjacent at least one gate spacer;

oxidizing the first interlayer dielectric material layer; and

annealing the first interlayer dielectric material layer.

2. The method of claim 1, wherein forming the first interlayer dielectric material layer comprises depositing the first interlayer dielectric material layer with a spin-on coating technique.

3. The method of claim 1, further including forming an adhesion liner adjacent the source/drain region and adjacent at least one gate spacer, prior to forming the first interlayer dielectric material layer.

4. The method of claim 1, wherein oxidizing the first interlayer dielectric material layer comprises heating the first interlayer dielectric material layer in a steam atmosphere.

5. The method of claim 4, wherein heating the first interlayer dielectric material layer in a steam atmosphere comprises heating the first interlayer dielectric material layer to a temperature of about 410 degrees Celsius in about a 93% steam atmosphere for about 2 hours.

6. The method of claim 1, wherein annealing the first interlayer dielectric material layer comprises annealing the first interlayer dielectric material layer with high density plasma in an inert atmosphere.

7. The method of claim 1, wherein oxidizing and annealing the first interlayer dielectric material layer shrinks the first interlayer dielectric material layer to exert a tensile strain on the source/drain region.

8. A method comprising:

forming a sacrificial non-planar transistor gate over a non-planar transistor fin;

depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin;

forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate;

forming a source/drain region;

removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin;

forming a gate dielectric adjacent the non-planar transistor fin within the gate trench;

depositing conductive gate material within the gate trench;

removing a portion of the conductive gate material to form a recess between the non-planar transistor gate spacers;

forming a capping dielectric structure within the recess;

forming a first interlayer dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and

oxidizing the first interlayer dielectric material layer; and

annealing the first interlayer dielectric material layer.

9. The method of claim 8, wherein forming the first interlayer dielectric material layer comprises depositing the first interlayer dielectric material layer with a spin-on coating technique.

10. The method of claim 8, further including forming an adhesion liner adjacent the source/drain region and adjacent at least one gate spacer, prior to forming the first interlayer dielectric material layer.

11. The method of claim 8, wherein oxidizing the first interlayer dielectric material layer comprises heating the first interlayer dielectric material layer in a steam atmosphere.

12. The method of claim 11, wherein heating the first interlayer dielectric material layer in a steam atmosphere comprises heating the first interlayer dielectric material layer to a temperature of about 410 degrees Celsius in about a 93% steam atmosphere for about 2 hours.

13. The method of claim 8, wherein annealing the first interlayer dielectric material layer comprises annealing the first interlayer dielectric material layer with high density plasma in an inert atmosphere.

14. The method of claim 8, further including planarizing the first interlayer dielectric material layer.

15. The method of claim 8, further including forming a contact through the at least one dielectric material to contact at least a portion of the source/drain region.

16. The method of claim 8, wherein oxidizing and annealing the first interlayer dielectric material layer shrinks the first interlayer dielectric material layer to exert a tensile strain on the source/drain region.

17. A microelectronic transistor, comprising:

a transistor gate including a gate electrode formed adjacent a substrate and a pair of gate spacers disposed on opposing sides of the gate electrode;

a source/drain region adjacent the transistor gate; and

a first interlayer dielectric material layer formed adjacent the substrate, adjacent the source/drain region, and adjacent at least one gate spacer, wherein the first interlayer dielectric material layer includes a densified portion formed proximate a first surface of the first interlayer dielectric material layer.

18. The microelectronic transistor of claim 17, wherein the transistor gate is non-planar.

19. The microelectronic transistor of claim 17, wherein the source/drain region is non-planar.

20. The microelectronic transistor of claim 17, further including a capping dielectric structure disposed adjacent the non-planar gate electrode and between the pair of gate spacers.