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INTERLAYER DIELECTRIC FOR NON-PLANAR TRANSISTORS

  • US 20140117425A1
  • Filed: 12/06/2011
  • Published: 05/01/2014
  • Est. Priority Date: 12/06/2011
  • Status: Active Grant
First Claim
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1. A method of fabricating a microelectronic transistor, comprising:

  • forming a transistor gate including a gate electrode adjacent a substrate and a pair of gates spacers on opposing sides of the gate electrode;

    forming a source/drain region;

    forming a first interlayer dielectric material layer adjacent the source/drain region and adjacent at least one gate spacer;

    oxidizing the first interlayer dielectric material layer; and

    annealing the first interlayer dielectric material layer.

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