INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE
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Accused Products
Abstract
A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.
8 Citations
27 Claims
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1-14. -14. (canceled)
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15. An integrated circuit, comprising:
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at least one first poly-silicon gate region including a first poly-silicon layer, a second poly-silicon layer, at least one first poly-silicon finger associated with the first poly-silicon layer, and at least one second poly-silicon finger associated with the second poly-silicon layer, wherein the first poly-silicon layer and the second poly-silicon layer are at least partially overlapping, and wherein the at least one first and the at least one second poly-silicon finger are orientated in a substantially orthogonal manner; and at least one second poly-silicon gate region including the first poly-silicon layer, wherein the at least one first poly-silicon gate region and the at least one second poly-silicon gate region each have different poly-silicon gate structures. - View Dependent Claims (17, 18, 19, 22, 23, 24, 25, 26, 27)
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16. (canceled)
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20-21. -21. (canceled)
Specification