BULK FINFET WITH PUNCHTHROUGH STOPPER REGION AND METHOD OF FABRICATION

• US 20140117462A1
• Filed: 10/31/2012
• Published: 05/01/2014
• Est. Priority Date: 10/31/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Ponoth, Shom, Sreenivasan, Ragvahasimhan
• Granted Patent: US 9,082,853 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

An improved bulk FinFET with a punchthrough stopper region, and method of fabrication are disclosed. The dopants used to form the punchthrough stopper are supplied from a shallow trench isolation liner. An anneal diffuses the dopants from the shallow trench isolation liner into the bulk substrate and lower portion of the fins, to form the punchthrough stopper region.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate;

a plurality of fins formed in the semiconductor substrate, wherein each fin has an upper portion and a lower portion;

a punchthrough stopper region disposed in the lower portion of each fin of the plurality of fins;

a doped shallow trench isolation liner disposed between each fin;

a shallow trench isolation region disposed between each fin;

a gate dielectric layer disposed over the plurality of fins; and

a gate region disposed over the gate dielectric layer.

2. The semiconductor structure of claim 1, wherein the doped shallow trench isolation liner is comprised of arsenic silicon glass.

3. The semiconductor structure of claim 1, wherein the doped shallow trench isolation liner is comprised of borosilicate glass.

4. The semiconductor structure of claim 1, wherein the doped shallow trench isolation liner has a thickness ranging from about 3 nanometers to about 10 nanometers.

5. The semiconductor structure of claim 1, wherein the shallow trench isolation region disposed between each fin is comprised of oxide.

6. The semiconductor structure of claim 1, wherein each fin of the plurality of fins has a total height ranging from about 50 nanometers to about 170 nanometers.

7. The semiconductor structure of claim 6, wherein the lower portion of each fin has a height ranging from about 0.4 times the total height to about 0.6 times the total height.

8. The semiconductor structure of claim 1, wherein the punchthrough stopper region is in the lower portion of each fin, and forms a contiguous region in the semiconductor structure, below a base of each fin.

9. The semiconductor structure of claim 1, wherein the gate dielectric layer is comprised of hafnium oxide.

10. The semiconductor structure of claim 1, wherein the gate region is comprised of polysilicon.

11. The semiconductor structure of claim 1, wherein the gate region is comprised of metal.

12. The semiconductor structure of claim 1, wherein the upper portion of each fin is narrower than the lower portion of each fin.

13. The semiconductor structure of claim 12, wherein the upper portion of each fin has a width ranging from about 30 nanometers to about 50 nanometers, and wherein the lower portion of each fin has a width ranging from about 40 nanometers to about 60 nanometers.

14. A method of forming a punchthrough stopper region on a bulk finFET, comprising:

depositing a shallow trench isolation liner over a semiconductor structure, wherein the semiconductor structure comprises a plurality of fins formed in a semiconductor substrate;

depositing a shallow trench isolation region over the shallow trench isolation liner;

recessing the shallow trench isolation region; and

annealing the semiconductor structure.

15. The method of claim 14, further comprising planarizing the shallow trench isolation region.

16. The method of claim 14, further comprising, depositing a nitride cap layer over the semiconductor structure prior to annealing the semiconductor structure.

17. The method of claim 14, wherein annealing the semiconductor structure comprises annealing for a duration ranging from about 1 millisecond to about 60 seconds at a temperature ranging from about 900 degrees Celsius to about 1300 degrees Celsius.

18. A method of forming a punchthrough stopper region on a bulk finFET, comprising:

performing a first etch to a first depth to form a plurality of fins on a semiconductor substrate;

forming a spacer on each side of each fin of the plurality of fins;

performing a second etch to a second depth to extend the length of the plurality of fins;

depositing a shallow trench isolation liner over the plurality of fins;

depositing a shallow trench isolation region over the shallow trench isolation liner;

recessing the shallow trench isolation region; and

annealing the bulk finFET.

19. The method of claim 18, wherein annealing the bulk finFET comprises annealing for a duration ranging from about 1 millisecond to about 60 seconds at a temperature ranging from about 900 degrees Celsius to about 1300 degrees Celsius.

20. The method of claim 19, wherein performing a first etch to a first depth comprises performing a reactive ion etch to a depth ranging from about 40 nanometers to about 80 nanometers, and wherein performing a second etch to a second depth comprises performing a reactive ion etch to a depth ranging from about 20 nanometers to about 60 nanometers.