SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INPUTTING MODIFIED COVERAGE DATA INTO A PIXEL SHADER

• US 20140118351A1
• Filed: 11/01/2012
• Published: 05/01/2014
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Uralsky, Yury, Moreton, Henry Packard
• Granted Patent: US 9,165,399 B2
• Time in Patent Office: Days
• US Class Current: 345/426
• CPC Class Codes: G06T 15/405 using Z-buffer
• CPC Class Codes: G06T 15/503 Blending, e.g. for anti-aliasing

Abstract

A system, method, and computer program product are provided for inputting modified coverage data into a pixel shader. In use, coverage data modified by a depth/stencil test is input into a pixel shader. Additionally, one or more actions are performed at the pixel shader, utilizing the modified coverage data.

Claims

1. A method, comprising:

inputting coverage data modified by a depth/stencil test into a pixel shader; and

performing one or more actions at the pixel shader, utilizing the modified coverage data.

2. The method of claim 1, wherein unmodified coverage data is modified by the depth/stencil test to create the coverage data modified by a depth/stencil test

3. The method of claim 2, wherein the unmodified coverage data includes raster coverage data.

4. The method of claim 2, wherein the unmodified coverage data includes an indication as to which subsamples within a multisampled pattern are covered by a generated primitive.

5. The method of claim 2, wherein the unmodified coverage data includes a coverage bitmask.

6. The method of claim 2, wherein the unmodified coverage data includes a bitmask indicating which subsamples within the multisampled pattern are covered by an input primitive.

7. The method of claim 2, wherein the unmodified coverage data is created by a rasterizer before the coverage data is modified by the depth/stencil test.

8. The method of claim 7, wherein the rasterizer provides the unmodified coverage data to the depth/stencil test module.

9. The method of claim 5, wherein the depth/stencil test modifies the coverage bitmask by turning off coverage within the coverage bitmask for subsamples within a multisampled pattern that fail the depth/stencil test.

10. The method of claim 2, wherein the unmodified coverage data is modified by the depth/stencil test within a pipeline running in early-Z (depth) mode, where the depth/stencil test is performed on the coverage data before such coverage data is sent to a pixel shader.

11. The method of claim 1, wherein the modified coverage data is input into the pixel shader utilizing a multiplexer.

12. The method of claim 1, wherein the pixel shader performs shading operations on a multisampled pattern in accordance with the modified coverage data.

13. The method of claim 1, wherein the pixel shader performs shading calculations at locations within a multisampled pattern that have not failed the depth/stencil test.

14. The method of claim 1, wherein the pixel shader stores the modified coverage data to memory.

15. The method of claim 1, wherein the pixel shader writes the modified coverage data to memory for later order-independent transparency (OIT) processing.

16. The method of claim 2, wherein the pixel shader receives both the coverage data modified by the depth/stencil test as well as the unmodified coverage data.

17. The method of claim 16, wherein the pixel shader chooses between the modified coverage data and the unmodified coverage data that has been received.

18. A computer program product embodied on a computer readable medium, comprising:

code for inputting coverage data modified by a depth/stencil test into a pixel shader; and

code for performing one or more actions at the pixel shader, utilizing the modified coverage data.

19. A system, comprising:

a processor for inputting coverage data modified by a depth/stencil test into a pixel shader, and performing one or more actions at the pixel shader, utilizing the modified coverage data.

20. The system of claim 19, wherein the processor is coupled to memory via a bus.