POWER FACTOR CORRECTION CIRCUIT AND METHOD FOR CONTROLLING POWER FACTOR CORRECTION

• US 20140119070A1
• Filed: 02/08/2013
• Published: 05/01/2014
• Est. Priority Date: 10/30/2012
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Um, Kee Ju, Suh, Bum Seok, Kim, Kwang Soo, Jeong, In Wha, Park, Min Gyu
• Granted Patent: US 9,019,735 B2
• Time in Patent Office: Days
• US Class Current: 363/45
• CPC Class Codes: H02M 1/342 Active non-dissipative snubbers
• CPC Class Codes: H02M 1/42 Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

Disclosed herein is a power factor correction circuit, including: a boost converter circuit in which a plurality of boost circuits including a boost inductor, a rectifying diode, and a boost switch are connected with each other; and a snubber circuit including a snubber inductor and a snubber switch so as to snubber the boost converter circuit. The snubber inductor is controlled so as to be turned on before the boost inductor is turned on to apply zero voltage to the boost inductor. It is possible to reduce switching loss occurring when the boost switch is turned on and increase efficiency of an AC-DC power supply apparatus.

Claims

1. A power factor correction circuit, comprising:

a boost converter circuit in which a plurality of boost circuits including a boost inductor, a rectifying diode, and a boost switch are connected with each other; and

a snubber circuit including a snubber inductor and a snubber switch so as to snubber the boost converter circuit.

2. The power factor correction circuit as set forth in claim 1, wherein the boost converter circuit further includes a boost capacitor.

3. The power factor correction circuit as set forth in claim 1, wherein the boost inductor has one terminal receiving current and the other terminal connected to the rectifying diode and the boost switch.

4. The power factor correction circuit as set forth in claim 1, wherein the boost converter circuit is configured by connecting the plurality of boost circuits in parallel.

5. The power factor correction circuit as set forth in claim 1, wherein the snubber circuit is connected with the boost switch in parallel.

6. The power factor correction circuit as set forth in claim 1, wherein the snubber switch is configured of any one of a transistor, a power MOSFET and an IGBT.

7. The power factor correction circuit as set forth in claim 1, wherein the snubber switch is controlled to be turned on before the boost switch is turned on.

8. The power factor correction circuit as set forth in claim 1, wherein when the boost switch is turned on, the snubber switch is controlled to substantially apply zero voltage switching.

32. A semiconductor chip including the power factor correction circuit as set forth in any one of claims 1 to 23.

9. A power factor correction circuit, comprising:

a boost converter circuit in which N boost circuits including a boost inductor, a rectifying diode, and a boost switch are connected with each other; and

a snubber circuit including N snubber inductors and N snubber switches so as to snubber the boost converter circuit,

wherein N is a natural number of 1 or more.

10. The power factor correction circuit as set forth in claim 9, wherein N boost inductors each have a phase difference of 360°

/N.

11. The power factor correction circuit as set forth in claim 9, wherein the boost inductor has one terminal receiving current and the other terminal connected to the rectifying diode and the boost switch.

12. The power factor correction circuit as set forth in claim 9, wherein the snubber circuit is configured by connecting a set in which one snubber inductor is connected with one snubber switch in series with N boost switches, respectively, in parallel.

13. The power factor correction circuit as set forth in claim 9, wherein at least one of the N snubber inductors is coupled with the boost inductor.

14. A power factor correction circuit, comprising:

a boost converter circuit in which N boost circuits including a boost inductor, a rectifying diode, and a boost switch are connected with each other; and

a snubber circuit including N snubber switches and M snubber inductors so as to snubber the boost converter circuit,

wherein N and M meet N>

M.

15. The power factor correction circuit as set forth in claim 14, wherein N boost inductors each have a phase difference of 360°

/N.

16. The power factor correction circuit as set forth in claim 14, wherein the boost inductor has one terminal receiving current and the other terminal connected to the rectifying diode and the boost switch.

17. The power factor correction circuit as set forth in claim 14, wherein at least two of the N snubber switches is directly connected with one snubber inductor to share a snubber inductor.

18. The power factor correction circuit as set forth in claim 17, wherein the snubber circuit is configured by connecting a set in which one snubber switch is connected with the shared snubber inductor with the boost switch in parallel.

19. The power factor correction circuit as set forth in claim 14, wherein at least one of the M snubber inductors is coupled with the boost inductor.

20. A power factor correction circuit, comprising:

a boost converter circuit in which N boost circuits including a boost inductor, a rectifying diode, and a boost switch are connected with each other,

wherein each boost inductor within the N boost circuits has a phase difference of 360°

/N and N is an integer of 2 or more.

21. The power factor correction circuit as set forth in claim 20, wherein the boost converter circuit further includes a boost capacitor.

22. The power factor correction circuit as set forth in claim 20, wherein the boost inductor has one terminal receiving current and the other terminal connected to the rectifying diode and the boost switch.

23. The power factor correction circuit as set forth in claim 20, wherein the boost converter circuit is configured by connecting N boost circuits, respectively, in parallel.

24. A power factor correction method, comprising:

performing a control to turn on a first snubber switch before a first boost switch driving a first boost inductor having a first phase is turned on; and

performing a control to turn on a second snubber switch before a second boost switch driving a second boost inductor having a second phase is turned on.

25. The power factor correction circuit method as set forth in claim 24, further comprising:

performing a control to turn on an N-th snubber switch before an N-th boost switch driving an N-th boost inductor having an N-th phase is turned on, wherein N is a natural number of 3 or more.

26. The power factor correction method as set forth in claim 24, wherein the first phase and the second phase have a predetermined phase difference.

27. The power factor correction method as set forth in claim 24, further comprising:

when the boost switch is turned on, controlling the snubber switch to substantially apply zero voltage switching.

28. A program readable medium on which a program enabling a processor to execute a power factor correction method is recorded, wherein the program includes:

a command executing a control to turn on a first snubber switch before a first boost switch driving a first boost inductor having a first phase is turned on; and

a command executing a control to turn on a second snubber switch before a second boost switch driving a second boost inductor having a second phase is turned on.

29. The program readable medium as set forth in claim 28, wherein the program further includes a command executing a control to turn on an N-th snubber switch before an N-th boost switch driving an N-th boost inductor having an N-th phase is turned on, wherein N is a natural number of 3 or more.

30. The program readable medium as set forth in claim 28, wherein the first phase and the second phase have a predetermined phase difference.

31. The program readable medium as set forth in claim 28, wherein when the boost switch is turned on, the program further includes a command controlling the snubber switch to substantially apply zero voltage switching.