Dual Mode Power Supply Controller with Current Regulation

• US 20140119078A1
• Filed: 10/31/2012
• Published: 05/01/2014
• Est. Priority Date: 10/31/2012
• Status: Active Grant

• Current Assignee: IDEAL Industries Lighting, LLC (Ideal Industries Incorporated)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Walters, Michael, Hu, Qingcong
• Granted Patent: US 9,484,805 B2
• Time in Patent Office: Days
• US Class Current: 363/89
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A power conversion circuit includes a voltage boost circuit including a boost inductor configured to generate an output voltage in response to an input voltage, and a boost controller configured to control operation of the voltage boost circuit. The boost controller is configured to control operation of the voltage boost circuit in response to a level of current in the boost inductor.

Claims

1. A power conversion circuit, comprising:

a voltage boost circuit including a boost inductor and being configured to generate an output voltage in response to an input voltage; and

a boost controller configured to control operation of the voltage boost circuit;

wherein the boost controller is configured to control operation of the voltage boost circuit in response to a level of current in the boost inductor.

2. The power conversion circuit of claim 1, wherein the boost controller is configured to compare the level of current in the boost inductor to a threshold level, and to change a state of a pulse width modulation signal that is supplied to the voltage boost circuit in response to the level of current in the boost inductor reaching the threshold level.

3. The power conversion circuit of claim 1, wherein the power conversion circuit is configurable to be operated in one of a hysteretic mode in which the level of current in the boost inductor is allowed to vary between a first low level and a first high level, and a critical current mode in which the level of current in the boost inductor is allowed to vary between a second low level and a second high level that follows a rectified input voltage.

4. The power conversion circuit of claim 3, wherein the boost controller is configured to generate an error signal in response to a load current and to generate the threshold level in response to the error signal.

5. The power conversion circuit of claim 1, wherein the boost controller is further configured to generate a first current (I_CS) that is representative of the current in the boost inductor, to generate a current sense signal (V_ICS) in response to the first current, to compare the current sense signal to a threshold voltage, and to change a state of the pulse width modulation signal in response to the current sense signal reaching the threshold voltage.

6. The power conversion circuit of claim 5, wherein the boost controller is further configured to generate a second current (I_HYS), to add the first current (I_CS) to the second current to generate a combined current (I_HYS+I_CS), to generate a combined voltage signal in response to the combined current, and to compare the combined voltage signal to the threshold voltage.

7. The power conversion circuit of claim 6, wherein the boost controller is configured to set the pulse width modulation signal to a first voltage level in response to the combined voltage signal falling below the threshold voltage and to reset the pulse width modulation signal to a second voltage level in response to the current sense signal rising above the threshold voltage.

8. The power conversion circuit of claim 7, wherein the boost controller is configured to generate an error signal in response to a load current and to generate the threshold voltage in response to the error signal.

9. The power conversion circuit of claim 7, wherein the boost controller comprises a pulse width modulation controller that is configured to receive the current sense signal, the combined voltage signal and the threshold voltage and responsively generate the pulse width modulation signal.

10. The power conversion circuit of claim 9, wherein the pulse width modulation controller comprises a first comparator configured to receive the current sense signal and the threshold voltage and to generate a RESET signal in response to a comparison of the current sense signal and the threshold voltage, a second comparator configured to receive the combined voltage signal and the threshold voltage and to generate a SET signal in response to a comparison of the combined voltage signal and the threshold voltage, and a data latch coupled to the first and second comparator and configured to control the pulse width modulation signal in response to the SET signal and the RESET signal.

11. The power conversion circuit of claim 10, wherein the boost controller further comprises a current sensing circuit configured to sense the level of the current in the boost inductor and to responsively generate the first current, the second current and the combined current.

12. The power conversion circuit of claim 11, wherein the current sensing circuit comprises a first current mirror configured to generate the first current, a second current mirror configured to generate the second current, and a combining node configured to combine the first current and the second current.

13. The power conversion circuit of claim 12, wherein the first current mirror is coupled to a current sense input that is coupled to the boost inductor, and wherein the second current mirror is coupled to a control input that is coupled to a reference voltage.

14. The power conversion circuit of claim 5, wherein the boost controller is further configured to generate a comparison signal in response to a load current, to generate a feedforward voltage signal in response to a feedforward signal (I_FF) that is representative of a level of a rectified input voltage signal, to multiply the comparison signal by the feedforward signal to obtain an error signal, and to compare the current sense signal to the error signal.

15. The power conversion circuit of claim 14, wherein the boost controller comprises a voltage clamp that is configured to clamp a level of the error signal between a high voltage and a low voltage.

16. The power conversion circuit of claim 14, wherein the boost controller is configured to set the pulse width modulation signal to a first voltage level in response to the current sense signal falling to zero and to reset the pulse width modulation signal to a second voltage level in response to the current sense signal rising above the error signal.

17. The power conversion circuit of claim 16, wherein the boost controller comprises pulse width modulation controller that is configured to receive the current sense signal, the combined voltage signal and the threshold voltage and responsively generate the pulse width modulation signal.

18. The power conversion circuit of claim 17, wherein the pulse width modulation controller comprises a first comparator configured to receive the current sense signal and the threshold voltage and to generate a RESET signal in response to a comparison of the current sense signal and the threshold voltage, a second comparator configured to receive the combined voltage signal and the threshold voltage and to generate a SET signal in response to a comparison of the combined voltage signal and the threshold voltage, and a data latch coupled to the first and second comparator and configured to control the pulse width modulation signal in response to the SET signal and the RESET signal.

19. The power conversion circuit of claim 10, wherein the boost controller further comprises a current sensing circuit configured to sense the level of the current in the boost inductor and to responsively generate the first current, the second current and the combined current.

20. The power conversion circuit of claim 19, wherein the current sensing circuit comprises a first current mirror configured to generate the first current, a second current mirror configured to generate the second current, and a combining node configured to combine the first current and the second current.

21. The power conversion circuit of claim 12, wherein the first current mirror is coupled to a current sense input that is coupled to the boost inductor, and wherein the second current mirror is coupled to a control input that is coupled to the rectified input signal.

22. The power conversion circuit of claim 1, wherein the boost controller is further configured to generate a current sense signal (I_CS) that is representative of the current in the boost inductor and to change a state of the pulse width modulation signal in response to the current sense signal falling below a first reference current or exceeding a second reference current.

23. The power conversion circuit of claim 1, wherein the boost controller is further configured to generate a first current (I_CS) that is representative of the current in the boost inductor, to generate a second current (I_HYS) having a predetermined level, to add the first current to the second current to form a combined current, and to change a state of the pulse width modulation signal in response to the combined current falling below a reference current or in response to the first current exceeding the reference current.

24. The power conversion circuit of claim 23, wherein the boost controller is configured to subtract the reference current from the first current to form a first differential current and to subtract the reference current from the second current to form a second differential current, to provide the first differential current at an input of a first logic circuit and to provide the second differential current to an input of a second logic circuit.

25. The power conversion circuit of claim 24, further comprising a data latch coupled to outputs of the first and second logic circuits, wherein an output of the data latch is provided as the pulse width modulation signal.

26. The power conversion circuit of claim 23, wherein the boost controller is configured to generate an error signal in response to a load current and to generate the reference current in response to the error signal.

27. The power conversion circuit of claim 1, wherein the boost controller is further configured to generate a first current (I_CS) that is representative of the current in the boost inductor, to generate an error signal in response to a load current, to generate first and second reference currents in response to the error signal, and to change a state of the pulse width modulation signal in response to the first current falling below the first reference current or in response to the first current exceeding the second reference current.

28. The power conversion circuit of claim 27, wherein the boost controller is further configured to generate a feedforward current (I_FF) in response to a rectified input voltage and to multiply the error signal by a level of the feedforward current.

29. The power conversion circuit of claim 27, wherein the boost controller is configured to subtract the first reference current from the first current to form a first differential current and to subtract the second reference current from the first current to form a second differential current, to provide the first differential current at an input of a first logic circuit and to provide the second differential current to an input of a second logic circuit.

30. The power conversion circuit of claim 28, further comprising a data latch coupled to outputs of the first and second logic circuits, wherein an output of the data latch is provided as the pulse width modulation signal.

31. A power conversion circuit, comprising:

a voltage boost circuit including a boost inductor and being configured to generate an output voltage in response to an input voltage; and

a boost controller configured to control operation of the voltage boost circuit in response to a level of current in the boost inductor;

wherein the power conversion circuit is configurable to be operated in one of a hysteretic mode in which the level of current in the boost inductor is allowed to vary between a first low level and a first high level, and a critical current mode in which the level of current in the boost inductor is allowed to vary between a second low level and a second high level that follows a rectified input voltage.

32. A power conversion circuit, comprising:

a voltage boost circuit including a boost inductor and a switch and being configured to generate an output voltage in response to an input voltage;

a current sensing circuit configured to sense a level of current in the boost inductor; and

a pulse width modulation circuit configured to generate a control signal that controls operation of the switch in response to the level of current in the boost inductor.

33. A method of operating a power conversion circuit including a voltage boost circuit having a boost inductor, the method comprising:

receiving an input voltage; and

controlling operation of the voltage boost circuit in response to a level of current in the boost inductor.

34. The method of claim 33, further comprising comparing the level of current in the boost inductor to a threshold level, and changing a state of a pulse width modulation signal that is supplied to the voltage boost circuit in response to the level of current in the boost inductor reaching the threshold level.

35. The method of claim 33, further comprising generating a first current (I_CS) that is representative of the current in the boost inductor, generating a current sense signal (V_ICS) in response to the first current, comparing the current sense signal to a threshold voltage, and changing a state of the pulse width modulation signal in response to the comparison.

36. The method of claim 35, further comprising generating a second current (I_HYS), adding the first current (I_CS) to the second current to generate a combined current (I_HYS+I_CS), generating a combined voltage signal in response to the combined current, and comparing the combined voltage signal to the threshold voltage.

37. The method of claim 36, further comprising setting the pulse width modulation signal to a first voltage level in response to the combined voltage signal falling below the threshold voltage and resetting the pulse width modulation signal to a second voltage level in response to the current sense signal rising above the threshold voltage.

38. The method of claim 37, further comprising generating an error signal in response to a load current and generating the threshold voltage in response to the error signal.

39. The method of claim 37, further comprising generating the pulse width modulation signal in response to the current sense signal, the combined voltage signal and the threshold voltage.

40. The method of claim 35, further comprising generating a comparison signal in response to a load current, generating a feedforward voltage signal in response to a feedforward signal (I_FF) that is representative of a level of a rectified input voltage signal, multiplying the comparison signal by the feedforward signal to obtain an error signal, and comparing the current sense signal to the error signal.

41. The method of claim 40, further comprising setting the pulse width modulation signal to a first voltage level in response to the current sense signal falling to zero and resetting the pulse width modulation signal to a second voltage level in response to the current sense signal rising above the error signal.

42. The method of claim 41, further comprising generating the pulse width modulation signal in response to the current sense signal, the combined voltage signal and the threshold voltage and responsively.

43. The method of claim 33, further comprising generating a current signal (I_CS) that is representative of the current in the boost inductor and changing a state of the pulse width modulation signal in response to the current signal falling below a first reference current or exceeding a second reference current.

44. The method of claim 33, further comprising generating a first current (I_CS) that is representative of the current in the boost inductor, generating a second current (I_HYS) having a predetermined level, adding the first current to the second current to form a combined current, and changing a state of the pulse width modulation signal in response to the combined current falling below a reference current or in response to the first current exceeding the reference current.

45. The method of claim 44, further comprising subtracting the reference current from the first current to form a first differential current, subtracting the reference current from the second current to form a second differential current, providing the first differential current at an input of a first logic circuit and providing the second differential current to an input of a second logic circuit.

46. The method of claim 43, further comprising generating an error signal in response to a load current and generating the reference current in response to the error signal.

47. The method of claim 33, further comprising generating a first current (I_CS) that is representative of the current in the boost inductor, generating an error signal in response to a load current, generating first and second reference currents in response to the error signal, and changing a state of the pulse width modulation signal in response to the first current falling below the first reference current or in response to the first current exceeding the second reference current.

48. The method of claim 47, further comprising generating a feedforward current (I_FF) in response to a rectified input voltage and multiplying the error signal by a level of the feedforward current.

49. The method of claim 47, further comprising subtracting the first reference current from the first current to form a first differential current, subtracting the second reference current from the first current to form a second differential current, providing the first differential current at an input of a first logic circuit and providing the second differential current to an input of a second logic circuit.