ADJUSTING PROGRAM AND ERASE VOLTAGES IN A MEMORY DEVICE
First Claim
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1. A memory array comprising:
- a first select gate;
a first edge cell arranged directly adjacent to and not in contact with the first select gate;
a second select gate; and
a second edge cell arranged directly adjacent to the second select gate, wherein during an erase operation, the first edge cell is configured to receive a first erase voltage and the second edge cell is configured to receive a second erase voltage different from the first erase voltage.
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Abstract
A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string.
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Citations
23 Claims
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1. A memory array comprising:
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a first select gate; a first edge cell arranged directly adjacent to and not in contact with the first select gate; a second select gate; and a second edge cell arranged directly adjacent to the second select gate, wherein during an erase operation, the first edge cell is configured to receive a first erase voltage and the second edge cell is configured to receive a second erase voltage different from the first erase voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory array comprising:
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a first select gate; a first edge cell arranged directly adjacent to and not in contact with the first select gate; a second select gate; and a second edge cell arranged directly adjacent to the second select gate, wherein during a programming operation, the first edge cell is configured to receive a first program voltage and the second edge cell is configured to receive a second program voltage different from the first program voltage. - View Dependent Claims (15, 16, 17, 18)
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19. A memory array comprising:
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a control gate of a first edge memory cell configured to receive a first voltage level during a selected type of operation of the memory array; and a control gate of a second edge memory cell configured to receive a second voltage level during the selected type of operation, wherein the first voltage level is different from the second voltage level. - View Dependent Claims (20, 21, 22, 23)
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Specification