Dynamic Bit Line Bias For Programming Non-Volatile Memory

• US 20140119126A1
• Filed: 10/25/2012
• Published: 05/01/2014
• Est. Priority Date: 10/25/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dutta, Deepanshu, Oowada, Ken, Higashitani, Masaaki, Mui, Man L.
• Granted Patent: US 8,953,386 B2
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.

Claims

1. A method for programming in a non-volatile storage device, comprising:

in a program operation, applying one or more initial program pulses to one non-volatile storage element;

during each program pulse of the one or more initial program pulses, setting a voltage of a bit line associated with the one non-volatile storage element at an initial level (0 V) which allows programming of the one non-volatile storage element;

determining when a threshold voltage of the one non-volatile storage element exceeds a lower verify level (VvaL, VvbL, VvcL) of a target data state (A, B, C) of the one non-volatile storage element; and

when the threshold voltage of the one non-volatile storage element exceeds the lower verify level, applying additional program pulses to the one non-volatile storage element, maintaining a count of a number of the additional program pulses which are applied to the one non-volatile storage element, and during the additional program pulses, setting the voltage of the bit line at one or more stepped up levels as a function of the count, the one or more stepped up levels are stepped up from the initial level and allow programming of the one non-volatile storage element.

2. The method of claim 1, wherein:

for one program pulse of the additional program pulses, the voltage of the bit line is stepped up by a step size which is a function of a step size of the one program pulse.

3. The method of claim 1, wherein:

the voltage of the bit line is stepped up by different step sizes during the additional program pulses.

4. The method of claim 1, wherein:

the voltage of the bit line is stepped up in three different program pulses of the additional program pulses.

5. The method of claim 1, wherein:

the voltage of the bit line is stepped up in non-adjacent program pulses of the additional program pulses, and not stepped up in a program pulse which is between the non-adjacent program pulses.

6. The method of claim 1, wherein:

the voltage of the bit line is set to a first stepped up level when a first program pulse of the additional program pulses is applied to the one non-volatile storage element;

the voltage of the bit line is set to a second stepped up level, higher than the first stepped up level, when a second program pulse of the additional program pulses is applied to the one non-volatile storage element; and

the voltage of the bit line is set to a third stepped up level, higher than the second stepped up level, when a third program pulse of the additional program pulses is applied to the one non-volatile storage element.

7. The method of claim 6, wherein:

the third stepped up level exceeds the second stepped up level by a respective step size;

the second stepped up level exceeds the first stepped up level by a respective step size; and

the first stepped up level exceeds the initial level by a step size which is larger than the respective step sizes of the second and third stepped up levels.

8. The method of claim 1, wherein:

the count is maintained by storing data in a set of latches associated with the one non-volatile storage element; and

the set of latches associated with the one non-volatile storage element is read before each program pulse of the additional program pulses to determine the count.

9. The method of claim 8, wherein:

the set of latches (QPW1, QPW2) associated with the one non-volatile storage element store four two-bit combinations indicating whether the count is zero, one, two or three.

10. The method of claim 8, wherein:

other non-volatile storage elements (240, 250) in the program operation reach a target data state (A) before the one non-volatile storage element reaches its target data state (B, C);

the set of latches associated with the one non-volatile storage element comprises a number N1>

=1 latches (QPW1, QPW2) which each store a bit of data, the count is determined from the N1 latches;

the set of latches associated with the one non-volatile storage element comprises a number N2>

=2 latches (LP, UP) which each store a bit of data, the target data state of the one non-volatile storage element is determined from the N2 latches;

when programming is not completed for the other non-volatile storage elements;

the N2 latches comprise one bit combination to identify the target data state of the one non-volatile storage element, and the one bit combination is different than another bit combination which identifies the target data state of the other non-volatile storage elements; and

when programming is completed for the other non-volatile storage elements;

the N2 latches comprise the another bit combination to identify the target data state of the one non-volatile storage element and to provide, in combination with the N1 latches, an additional value for the count.

11. The method of claim 10, wherein:

the count is not based on the N2 latches when the programming of the other non-volatile storage elements is not yet complete.

12. The method of claim 1, further comprising:

determining when the threshold voltage of the one non-volatile storage element exceeds a higher verify level; and

when the threshold voltage of the one non-volatile storage element exceeds the higher verify level, applying a next program pulse to the one non-volatile storage element, and during the next program pulse, setting the voltage of the bit line at a level which inhibits programming of the one non-volatile storage element.

13. The method of claim 1, wherein:

the voltage of the bit line is stepped up until a maximum level which allows programming of the one non-volatile storage element is reached, after which the voltage of the bit line is set at the maximum level during each of one or more subsequent program pulses which are applied to the one non-volatile storage element, until the threshold voltage of the one non-volatile storage element exceeds a higher verify level of the target data state.

14. A non-volatile storage system, comprising:

a set of non-volatile storage elements in communication with a word line;

a respective bit line associated with each non-volatile storage element; and

a control circuit, the control circuit;

sets a voltage of one of the respective bit lines which is associated with one non-volatile storage element at an initial level which allows programming of the one non-volatile storage element during one or more initial program pulses which are applied to the word line when a threshold voltage of the one non-volatile storage element is verified to be below a lower verify level, and sets the voltage of the bit line at different stepped up levels which allow programming of the one non-volatile storage element during additional program pulses which are applied to the word line when the threshold voltage of the one non-volatile storage element is verified to be between the lower verify level and a higher verify level.

15. The non-volatile storage system of claim 14, wherein:

the different stepped up levels increase until a maximum level which allows programming of the one non-volatile storage element is reached, after which the voltage of the bit line is set at the maximum level during each of one or more additional program pulses which are applied to the word line until the threshold voltage of the one non-volatile storage element is verified to exceed the higher verify level, the maximum level.

16. The non-volatile storage system of claim 14, wherein:

the control circuit stores data indicating a count of the additional program pulses which have been applied to the one non-volatile storage element after the threshold voltage of the one non-volatile storage element is verified to exceed the lower verify level, and sets the voltage of the bit line to the different stepped up levels based on the data.

17. The non-volatile storage system of claim 14, further comprising:

first and second latches associated with the one non-volatile storage element, the control circuit;

sets a first bit combination in the first and second latches after the threshold voltage of the one non-volatile storage element is verified to exceed the lower verify level and before a first program pulse of the additional program pulses is applied to the word line, the first bit combination is associated with a first stepped up level of the different stepped up levels, sets a second bit combination in the first and second latches after the first program pulse and before a second program pulse of the additional program pulses is applied to the word line, the second bit combination is associated with a second stepped up level of the different stepped up levels and decides to set the voltage of the bit line at one of the different stepped up levels in response to a read of the first and second latches, and sets a third bit combination in the first and second latches after the second program pulse and before a third program pulse of the additional program pulses is applied to the word line, the third bit combination is associated with a third stepped up level of the different stepped up levels.

18. A method for programming in a non-volatile storage device, comprising:

performing one or more program-verify iterations for a non-volatile storage element in a program operation, each program-verify iteration comprising a program portion and a verify portion;

applying an initial voltage to a bit line associated with the non-volatile storage element during the program portion of each of the one or more program-verify iterations;

detecting when the non-volatile storage element passes a first verify test of one of the verify portions of the one or more program-verify iterations; and

in response to the detecting when the non-volatile storage element passes the first verify test;

performing a first next program-verify iteration of the program operation, the first next program-verify iteration comprising a program portion and a verify portion;

applying a first stepped up voltage to the bit line during the program portion of the first next program-verify iteration;

performing a second next program-verify iteration of the program operation, the second next program-verify iteration comprising a program portion and a verify portion; and

applying a second stepped up voltage to the bit line during the program portion of the second next program-verify iteration, where the initial voltage, the first stepped up voltage and the second stepped up voltage allow programming of the non-volatile storage element.

19. The method of claim 18, further comprising:

in response to the detecting when the non-volatile storage element passes the first verify test;

performing a third next program-verify iteration of the program operation, the third next program-verify iteration comprising a program portion and a verify portion; and

applying a third stepped up voltage to the bit line during the program portion of the third next program-verify iteration, the third stepped up voltage allows programming of the non-volatile storage element.

20. The method of claim 18, further comprising:

detecting when the non-volatile storage element passes a second verify test of the program operation; and

in response to the detecting when the non-volatile storage element passes the second verify test;

performing another program-verify iteration of the program operation, the another program-verify iteration comprising a program portion and a verify portion; and

applying a voltage to the bit line which inhibits programming of the non-volatile storage element during the program portion of the another program-verify iteration.