Scalable Multifunction Serial Link Interface

• US 20140119463A1
• Filed: 10/31/2012
• Published: 05/01/2014
• Est. Priority Date: 10/29/2012
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Masse, Yves Michel Marie, Badi, Eric Louis Pierre, Avoinne, Christophe Denis Bernard
• Application Number:
  US13/665,919
• Publication Number:
  US 20140119463A1
• Time in Patent Office: Days
• US Class Current: 375/259
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission

Abstract

An integrated circuit includes two or more communication controllers and a plurality of point to point serial communication lanes for communication external to the integrated circuit. A programmable cross-point circuit allows different sets of serial communication lanes to be coupled at different times to the communication controllers in order to optimize performance of different applications.

Claims

1. A digital system comprising an integrated circuit, wherein the integrated circuit comprises:

a plurality of serial transmit lane drivers coupled to pins of the integrated circuit (IC);

a plurality of serial receive lane receivers coupled to pins of the IC;

a plurality of communication controllers each having a physical adaptor wherein each physical adaptor has a plurality of serial lane terminals, wherein a portion of the serial lane terminals are for transmitting and a portion of the serial lane terminals are for receiving;

a programmable multiplexor coupled between the plurality of transmit lane drivers and the plurality of transmit lane terminals on the plurality of communication controllers;

a programmable demultiplexor coupled between the plurality of receive lane receivers and the plurality of receive lane terminals on the plurality of communication controllers; and

a control module coupled to the multiplexor and to the demultiplexor, wherein the control module is operable to program the multiplexor to couple each transmit lane terminal to a selected one of the plurality of transmit lane drivers, and to program the demultiplexor to couple each receive lane terminal to a selected one of the plurality of receive lane receivers.

2. The digital system of claim 1, wherein the plurality of transmit lanes and the plurality of receive lanes are M-PHY lanes.

3. The digital system of claim 1, wherein one of the plurality of communication controllers is operable to use a portion of its transmit link terminals for a first application, and a different portion of it'"'"'s transmit link terminals for a second application.

4. The digital system of claim 1, wherein the control module is operable to program the multiplexor and the demultiplexor to couple a first set of serial transmit lane drivers and serial receive lane receivers to the lane terminals of a first communication controller of the plurality of communication controllers for a first period of time and to couple a different set of serial transmit lane drivers and serial receive lane receivers to the lane terminals of the first communication controller for a second period of time.

5. The digital system of claim 1, wherein the control module is operable to program the multiplexor to couple a number of serial transmit lane drivers to the lane terminals of a first communication controller of the plurality of communication controllers and to program the demultiplexor to couple a different number of serial receive lane receivers to the lane terminals of the first communication controller.

6. The digital system of claim 1 being a smart phone, wherein the digital system comprises a second integrated circuit coupled to the IC via a plurality of transmission lines coupled to the pins of the IC that are coupled to the receive lane receivers and to the transmit lane drivers.

7. A method for operating a system having an integrated circuit coupled to a plurality of point to point serial communication lanes for communication with other integrated circuits, wherein the method comprises:

initializing the integrated circuit when the integrated circuit is powered on;

configuring a cross-point interconnect circuit to allocate a first portion of the plurality of point to point serial communication lanes for use by a first communication controller in the integrated circuit and a second portion of the plurality of point to point serial communication lanes for use by a second communication controller in the integrated circuit; and

transmitting and receiving data via the first communication controller using the first portion of serial communication lanes and via the second communication controller using the second portion of serial communication lanes.

8. The method of claim 7, wherein the plurality of point to point serial communication lanes comprise transmit lanes and receive lanes, and wherein the cross-point interconnect circuit is configured to allocate the first portion to have a number of transmit lanes and a different number of receive lanes.

9. The method of claim 7, wherein configuring the cross-point interconnect circuit is performed by software instructions executed by a central processing unit (CPU) within the integrated circuit.

10. The method of claim 7, wherein the plurality of communication lanes are M-PHY lanes.

11. The method of claim 7, further comprising reconfiguring the cross-point circuit to allocate a third portion of the plurality of point to point serial communication lanes for use by the first communication controller and a fourth portion of the plurality of point to point serial communication lanes for use by the second communication controller;

and

transmitting and receiving data via the first communication controller using the third portion of serial communication lanes and via the second communication controller using the fourth portion of serial communication lanes.

12. The method of claim 11, wherein transmitting and receiving data via the first communication controller using the first portion of serial communication lanes and via the second communication controller using the second portion of serial communication lanes is performed for a first period of time, and

wherein transmitting and receiving data via the first communication controller using the third portion of serial communication lanes and via the second communication controller using the fourth portion of serial communication lanes is performed for a second period of time.

13. A digital system comprising an integrated circuit, wherein the integrated circuit comprises:

a plurality of serial transmit lane drivers coupled to pins of the integrated circuit (IC);

a plurality of serial receive lane receivers coupled to pins of the IC;

a plurality of communication controllers each having a physical adaptor wherein each physical adaptor has a plurality of serial lane terminals, wherein a portion of the serial lane terminals are for transmitting and a portion of the serial lane terminals are for receiving;

means for initializing the integrated after a power reset; and

means for allocating a first portion of the plurality of serial transmit lane drivers and serial receive lane receivers for use by a first one of the plurality of communication controller and a second portion of the plurality of serial transmit lane drivers and serial receive lane receivers for use by a second one of the plurality of communication controllers.

14. The digital system of claim 13, further comprising:

means for reallocating at a different time a third portion of the plurality of serial transmit lane drivers and serial receive lane receivers for use by the first communication controller and a fourth portion of the plurality of point to point serial transmit lane drivers and serial receive lane receivers for use by the second communication controller.

15. The digital system of claim 13, wherein the means for allocating is operable to allocate a number of serial transmit lane drivers to the lane terminals of a first communication controller of the plurality of communication controllers and allocate a different number of serial receive lane receivers to the lane terminals of the first communication controller.