SHIFT REGISTER AND METHOD FOR DRIVING THE SAME, GATE DRIVING DEVICE AND DISPLAY DEVICE

• US 20140119491A1
• Filed: 10/28/2013
• Published: 05/01/2014
• Est. Priority Date: 10/29/2012
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Liu, Yaohu
• Application Number:
  US14/064,295
• Publication Number:
  US 20140119491A1
• Time in Patent Office: Days
• US Class Current: 377/64
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The embodiments of the present invention provide a shift register and a method for driving the same, a gate driving device and a display device. A charging unit, a pull-up unit, a pull-down unit, a gate signal input terminal, a DC low level signal input terminal, a gate signal output terminal and a first, a second, a third, a fourth clock signal input terminals are arranged in the shift register, so that the gate driving structure is simplified and the power consumption of the gate driving is reduced.

Claims

1. A shift register, comprising a charging unit, a pull-up unit, a pull-down unit, a gate signal input terminal, a DC low level signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a fourth clock signal input terminal and a gate signal output terminal, wherein

the charging unit is coupled to the gate signal input terminal, the first clock signal input terminal, the pull-up unit and the pull-down unit respectively so as to control a potential of a pull-up node as a high level during a charging phase;

the pull-up unit is coupled to the charging unit, the pull-down unit, the second clock signal input terminal and the gate signal output terminal respectively so as to output a high level signal input by the second clock signal input terminal to the gate signal output terminal during an output phase; and

the pull-down unit is coupled to the charging unit, the pull-up unit, the DC low level signal input terminal, the third clock signal input terminal and the fourth clock signal input terminal respectively so as to control potentials of the pull-up node and the gate signal output terminal as a low level during a reset phase and a reset maintaining phase.

2. The shift register according to claim 1, wherein the charging unit comprises a first thin film transistor, wherein the source of the first thin film transistor is coupled to the gate signal input terminal, the gate of the first thin film transistor is coupled to the first clock signal input terminal, and the drain of the first thin film transistor is coupled to the pull-up unit and the pull-down unit respectively via the pull-up node.

3. The shift register according to claim 1, wherein the charging unit comprises a first thin film transistor and a second thin film transistor, wherein

the source of the first thin film transistor is coupled to the gate signal input terminal, the gate of the first thin film transistor is coupled to the first clock signal input terminal, and the drain of the first thin film transistor is coupled to the pull-up unit and the pull-down unit respectively via the pull-up node;

the source and the gate of the second thin film transistor are coupled to the gate signal input terminal, the drain of the second thin film transistor is coupled to the pull-up unit and the pull-down unit respectively via the pull-up node.

4. The shift register according to claim 1, wherein the pull-up unit comprises a third thin film transistor, wherein the source of the third thin film transistor is coupled to the second clock signal input terminal, the gate of the third thin film transistor is coupled to the charging unit and the pull-down unit respectively via the pull-up node, and the drain of the third thin film transistor is coupled to the gate signal output terminal and the pull-down unit respectively.

5. The shift register according to claim 4, wherein the pull up unit further comprises a storage capacitor, wherein a first terminal of the storage capacitor is coupled to the gate of the third thin film transistor, the pull up unit and the pull-down unit via the pull-up node, while a second terminal of the storage capacitor is coupled to the drain of the third thin film transistor, the gate signal output terminal and the pull-down unit respectively.

6. The shift register according to claim 1, wherein the pull-down unit comprises a first pull-down unit and a second pull-down unit, wherein

the first pull-down unit is coupled to the third clock signal input terminal and the DC low level signal input terminal respectively so as to control potentials of the pull-up node and the gate signal output terminal as a low level during the reset phase;

and

the second pull-down unit is coupled to the fourth clock signal input terminal and the DC low level signal input terminal respectively so as to control potentials of the pull-up node and the gate signal output terminal as a low level during the reset maintaining phase.

7. The shift register according to claim 6, wherein the first pull-down unit comprises a fourth thin film transistor and a fifth thin film transistor, wherein

the source of the fourth thin film transistor is coupled to the charging unit and the pull-up unit respectively via the pull-up node, the gate of the fourth thin film transistor is coupled to the third clock signal input terminal, the drain of the fourth thin film transistor is coupled to the DC low level signal input terminal;

and

the source of the fifth thin film transistor is coupled to the pull-up unit and the gate signal output terminal respectively via the pull-up node, the gate of the fifth thin film transistor is coupled to the third clock signal input terminal, and the drain of the fifth thin film transistor is coupled to the DC low level signal input terminal.

8. The shift register according to claim 6, wherein the second pull-down unit comprises a sixth thin film transistor and a seventh thin film transistor, wherein

the source of the sixth thin film transistor is coupled to the pull-up unit and the gate signal input terminal respectively, the gate of the sixth thin film transistor is coupled to the fourth clock signal input terminal and the drain of the sixth thin film transistor is coupled to the DC low level signal input terminal;

and

the source of the seventh thin film transistor is coupled to the charging unit and the pull-up unit respectively via the pull-up node, the gate of the seventh thin film transistor is coupled to the fourth clock signal input terminal, and the drain of the seventh thin film transistor is coupled to the DC low level signal input terminal.

9. The shift register according to claim 6, wherein the shift register further comprises a DC high level signal input terminal.

10. The shift register according to claim 9, wherein the first pull-down unit comprises a fourth thin film transistor, a fifth thin film transistor, an eighth thin film transistor and a tenth thin film transistor, wherein

the source of the fourth thin film transistor is coupled to the charging unit, the pull-up unit and the gate of the tenth thin film transistor respectively via the pull-up node, the gate of the fourth thin film transistor is coupled to the drain of the eighth thin film transistor and the source of the tenth thin film transistor respectively, and the drain of the fourth thin film transistor is coupled to the DC low level signal input terminal;

the source of the fifth thin film transistor is coupled to the pull-up unit and the gate signal output terminal respectively, the gate of the fifth thin film transistor is coupled to the drain of the eighth thin film transistor and the source of the tenth thin film transistor respectively, and the drain of the fifth thin film transistor is coupled to the DC low level signal input terminal;

the source of the eighth thin film transistor is coupled to the DC high level signal input terminal, the gate of the eighth thin film transistor is coupled to the third clock signal input terminal, and the drain of the eighth thin film transistor is coupled to the gate of the fourth thin film transistor, the gate of the fifth thin film transistor and the source of the tenth thin film transistor respectively; and

the drain of the tenth thin film transistor is coupled to the DC low level signal input terminal.

11. The shift register according to claim 9, wherein the second pull-down unit comprises a sixth thin film transistor, a seventh thin film transistor, a ninth thin film transistor and an eleventh thin film transistor, wherein

the source of the sixth thin film transistor is coupled to the pull-up unit and the gate signal output terminal respectively, the gate of the sixth thin film transistor is coupled to the drain of the ninth thin film transistor and the source of the eleventh thin film transistor respectively, the drain of the sixth thin film transistor is coupled to the DC low level signal input terminal;

the source of the seventh thin film transistor is coupled to the charging unit, the pull-up unit and the gate of the eleventh thin film transistor respectively via the pull-up node, the gate of the seventh thin film transistor is coupled to the drain of the ninth thin film transistor and the source of the eleventh thin film transistor respectively, the drain of the seventh thin film transistor is coupled to the DC low level signal input terminal;

the source of the ninth thin film transistor is coupled to the DC high level signal input terminal, the gate of the ninth thin film transistor is coupled to the fourth clock signal input terminal, the drain of the ninth thin film transistor is coupled to the gate of the sixth thin film transistor, the gate of the seventh thin film transistor and the source of the eleventh thin film transistor respectively; and

the drain of the eleventh thin film transistor is coupled to the DC low level signal input terminal.

13. A gate driving device, comprising multiple stages of shift registers according to claim 1;

except for the last stage of shift registers, each gate signal output terminal of remaining stages of shift registers is coupled to a gate signal input terminal of the next stage of shift registers.

14. A display device, comprising the gate driving device according to claim 13.

12. A method for driving a shift register, comprising:

during a charging phase, a gate signal input terminal inputting a gate signal, a first clock signal input terminal inputting a high level, a second, a third, a fourth clock signal input terminals inputting a low level, a charging unit controlling a potential of a pull-up node as a high level and starting to charge;

during an output phase, the gate signal input terminal completing inputting, the first, the third and the fourth clock signal input terminals inputting a low level, the second clock signal input terminal inputting a high level, a pull-up unit outputting the high level signal input by the second clock signal input terminal to a gate signal output terminal;

during a reset phase, the first, the second, the fourth clock signal input terminals inputting a low level, the third clock signal input terminal inputting a high level, a pull-down unit controlling potentials of a pull-up node and the gate signal output terminal as a low level; and

during a reset maintaining phase, the first, the second, the third clock signal input terminals inputting a low level, the fourth clock signal input terminal inputting a high level, the pull-down unit continuously controlling the potentials of the pull-up node and the gate signal output terminal as a low level.