TRENCHED POWER MOSFET WITH ENHANCED BREAKDOWN VOLTAGE AND FABRICATION METHOD THEREOF

• US 20140120670A1
• Filed: 03/07/2013
• Published: 05/01/2014
• Est. Priority Date: 08/13/2012
• Status: Active Grant

• Current Assignee: Super Group Semiconductor Co., Ltd.
• Original Assignee: Great Power Semiconductor Corp.
• Inventors: YEH, CHUN-YING
• Granted Patent: US 9,214,531 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A trenched power semiconductor device with enhanced breakdown voltage is provided. The trenched power semiconductor device has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region is extended to the bottom of the body region. A conductive structure is electrically connected to the heavily doped region and the source region.

Claims

1. A fabrication method of a trenched power semiconductor device with enhanced breakdown voltage at least comprising steps of:

(a) providing a substrate;

(b) forming at least two gate trenches in the substrate;

(c) forming a first dielectric layer lining inner surfaces of the gate trenches;

(d) forming a first polysilicon structure in the gate trenches;

(e) forming at least a first trench between the neighboring gate trenches;

(f) forming a second polysilicon structure of a first conductive type in a lower portion of the first trench;

(g) forming a body region of the first conductive type between the gate trenches, the first trench being extended to the substrate below the body region, and the second polysilicon structure being spaced from the body region with a predetermined distance and spacing from the body region with a predetermined distance;

(h) forming a source region of a second conductive type in an upper portion of the body region;

(i) forming an interlayer dielectric layer on the first polysilicon structure to define a source contact window aligned to the first trench;

(j) forming at least a heavily doped region of the first conductive type in the body region; and

(k) forming a source metal layer in the source contact window for electrically connecting to the heavily doped region and the source region.

2. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, after the step of forming the second polysilicon structure of the first conductive type, further comprising a step of forming a dielectric structure, which at least extends upward to the body region, in the first trench.

3. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the gate trenches and the first trench are simultaneously formed in the substrate.

4. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 2, wherein the step of forming the dielectric structure comprises:

forming a dielectric layer covering the interlayer dielectric layer and filling the first trench; and

removing a portion of the dielectric layer outside the first trench and expanding a width of the source contact window by etching.

5. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the steps of the forming the heavily doped region and the source region include two ion implantation steps for implanting dopants of the first conductive type and that of the second conductive type respectively, and implantation areas of the two ion implantation steps are partly overlapped for forming the heavily doped region and the source region alternatively arrayed on the body region.

6. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the step of forming the heavily doped region is to implant first conductive type dopants into the body region through the source contact window, and the heavily doped region is extended to the substrate below the body region.

7. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the step of forming the heavily doped region includes:

forming a heavily doped polysilicon structure on the dielectric structure; and

thermal diffusing dopants in the heavily doped polysilicon structure to the body region for forming the heavily doped region adjacent to the heavily doped polysilicon structure.

8. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the step of forming the first trench is later than the step of forming the source region in the upper portion of the body region, and the first trench penetrates the body region.

9. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, wherein the step of forming the first trench is prior to the step of forming the body region, a depth of the first trench is greater than that of the gate trench, and the step of forming the second polysilicon structure is prior to the step of forming the first polysilicon structure.

10. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, after the step of forming the second polysilicon structure, further comprising a step of forming a third polysilicon structure of the second conductive type in the first trench, and the third polysilicon structure being located above the second polysilicon structure and at least extended upward to the body region.

11. The fabrication method of the trenched power semiconductor device with enhanced breakdown voltage of claim 1, after the step of forming the second polysilicon structure of the first conductive type, further comprising a step of filling a metal plug in the first trench, and the metal plug being located above the second polysilicon structure and at least extended upward to the body region.