Methods for Selective and Conformal Epitaxy of Highly Doped Si-containing Materials for Three Dimensional Structures

• US 20140120678A1
• Filed: 10/25/2013
• Published: 05/01/2014
• Est. Priority Date: 10/29/2012
• Status: Abandoned Application

• Current Assignee: Matheson Tri-Gas Incorporated (Mitsubishi Chemical Group Corp.)
• Original Assignee: Matheson Tri-Gas Incorporated (Mitsubishi Chemical Group Corp.)
• Inventors: Shinriki, Manabu, Brabant, Paul, Chung, Keith Jr.
• Application Number:
  US14/063,118
• Publication Number:
  US 20140120678A1
• Time in Patent Office: Days
• US Class Current: 438/283
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present invention addresses the key challenges in FinFET fabrication, that is, the fabrications of thin, uniform fins and also reducing the source/drain series resistance. More particularly, this application relates to FinFET fabrication techniques utilizing tetrasilane to enable conformal deposition with high doping using phosphate, arsenic and boron as dopants thereby creating thin fins having uniform thickness (uniformity across devices) as well as smooth, vertical sidewalls, while simultaneously reducing the parasitic series resistance.

Claims

1. A method for forming an epitaxial film on a three-dimensional structure in a chemical vapor deposition system, comprising:

providing a three-dimensional structure disposed within a chamber;

introducing a silicon precursor to said chamber at a temperature of less than 600°

C., wherein said silicon precursor is accompanied with a carrier gas wherein said carrier gas has a flow rate of 10 to 200 times greater than the flow rate of said silicon precursor; and

forming an epitaxial film comprising multiple epilayers by way of a cyclical deposition and etch process wherein each epilayer is formed as a result of (i) exposing said three-dimensional structure to a process gas containing said silicon precursor to deposit a silicon-containing epilayer across the surfaces of said three-dimensional structure wherein said process carrier gas flows at a rate of about 100 to 2000 times greater than said silicon precursor and (ii) exposing said deposited silicon layer to an etchant gas so that the net growth of each epilayer is no great than 5-25 Å

per cycle.

2. The method of claim 1, wherein said three-dimensional structure is a FinFET device.

3. The method of claim 1, further comprising introducing a carbon precursor in combination with said silicon precursor.

4. The method of claim 1, further comprising introducing a germane precursor in combination with said silicon precursor.

5. The method of claim 3, further comprising introducing a germane precursor in combination with said silicon precursor.

6. The method of claim 1, wherein the germane precursor is selected from the group consisting of GeH₄ and Ge₂H₆.

7. The method of claim 1, wherein said silicon precursor is tetrasilane.

8. The method of claim 1, wherein said silicon precursor is a combination of one or more of the following:

n-tetrasilane, iso-tetrasilane, and/or cyclo-tetrasilane.

9. The method of claim 7, wherein said tetrasilane introduced to said chamber has a purity level in the range of approximately 95% to 99.9%.

10. The method of claim 7, wherein said tetrasilane introduced to said chamber has oxygenated impurities of less than 2000 ppm.

11. The method of claim 1, wherein said carbon precursor as introduced to said chamber has a purity level in the range of approximately 97% to approximately 99.9%.

12. The method of claim 1, wherein said a carbon precursor as introduced to said chamber has oxygenated impurities of less than 100 ppm.

13. The method of claim 3, wherein the carbon precursor is selected from the group consisting of tetramethyldisilane (TMDS), monosilylmethane, disilylmethane, trisilylmethane, tetrasilylmethane, monomethyl silane, dimethyl silane and 1,3-disilabutane, monomethyl silane (MMS), dimethyl silane, methylsilane, dimethylsilane, ethylsilane, methane, ethylene, ethyne, propane, propene, butyne, dodecamethylcyclohexasilane, and tetramethyldisilane.

14. The method of claim 3, wherein the carbon precursor comprises a formula Si_xH_y(CH₃)_z, where x is an integer in the range of 1 to 6 and where y and z are each an independently integer in the range of 0 to 6.

15. The method of claim 1, wherein said chamber has a temperature in the range of about 250°

C. to about 600°

C.

16. The method of claim 1, wherein said chamber has a pressure of about 100 milliTorr to about 10 Torr.

17. The method of claim 1, wherein a dopant is introduced into the chamber in combination with said silicon precursor.

18. The method of claim 17, wherein said dopant is selected from the group consisting of AsH₃, PH₃, B₂H₆, boron, arsenic, phosphorous, gallium and aluminum.

19. The method of claim 16, wherein said epitaxial film contains a dopant in the range of 1E+20 atoms/cm³-5E+21 atoms/cm³.

20. The method of claim 2, wherein said epilayers are periodically exposed to an HCl etching gas purified to about 10 ppb under a pressure in the range of 100-700 Torr wherein said FinFET device comprises two or more fins have vertical surface wherein said epilayers forming on the vertical surface of said fins remain vertical.

21. The method of claim 20, wherein the growth of said epilayers is stopped leaving a space between each Fin.

22. The method of claim 20, wherein the growth of said epilayers continues until said epilayers merge into one contiguous epitaxial layer.

23. A method for forming an epitaxial film on a FinFET device in a chemical vapor deposition system, comprising:

providing the FinFET device disposed within a chamber;

introducing a silicon precursor to said chamber at a temperature of less than 600°

C., wherein said silicon precursor is accompanied with a carrier gas wherein said carrier gas has a flow rate of 10 to 200 times greater than the flow rate of said a silicon precursor;

forming an epitaxial film comprising multiple epilayers by way of a cyclical deposition and etch process wherein each epilayer is formed as a result of (i) exposing said FinFET device to a process gas containing said silicon precursor to deposit a silicon-containing epilayer across the surfaces of the FinFET device wherein said process carrier gas flows at a rate of about 100 to 2000 times greater than said silicon precursor and (ii) exposing said deposited silicon layer to an etchant gas so that the net growth of each epilayer is no great than 5-25 Å

per cycle; and

exposing the epitaxial layers periodically to an HCl etching gas purified to about 10 ppb under a pressure in the range of 100-700 Torr wherein said FinFET device comprises two or more fins have vertical surface wherein said epilayers forming on the vertical surface of the fins remain vertical.

24. A method for forming an epitaxial film on a FinFET device in a chemical vapor deposition system, comprising:

providing the FinFET device disposed within a chamber;

introducing tetrasilane to said chamber at a temperature of less than 600°

C., wherein said tetrasilane is accompanied with a carrier gas wherein said carrier gas has a flow rate of 10 to 200 times greater than the flow rate of said tetrasilane;

forming an epitaxial film comprising multiple epilayers by way of a cyclical deposition and etch process wherein each epilayer is formed as a result of (i) exposing said FinFET device to a process gas containing said silicon precursor to deposit a silicon-containing epilayer across the surfaces of the FinFET device wherein said process carrier gas flows at a rate of about 100 to 2000 times greater than said tetrasilane and (ii) exposing said deposited tetrasilane layer to an etchant gas so that the net growth of each epilayer is no great than 5-25 Å

per cycle; and

exposing the epitaxial layers periodically to an HCl etching gas purified to about 10 ppb under a pressure in the range of 100-700 Torr wherein said FinFET device comprises two or more fins have vertical surface wherein said epilayers forming on the vertical surface of the fins remain vertical.