Method of protecting sidewall surfaces of a semiconductor device

• US 20140120720A1
• Filed: 10/21/2013
• Published: 05/01/2014
• Est. Priority Date: 11/03/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: ENGELHARDT, Manfred
• Granted Patent: US 9,012,325 B2
• Time in Patent Office: Days
• US Class Current: 438/669
• CPC Class Codes: H01L 21/28506 of conductive layers
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304

Abstract

One or more embodiments relate to a method of making a semiconductor structure, comprising: forming a opening partially through a semiconductor substrate, the opening including an upper portion and a lower portion; forming a first dielectric layer over a sidewall surface of the upper portion, wherein the first dielectric layer does not overlie a sidewall surface of the lower portion; and forming a conductive material over a sidewall surface of the first dielectric layer, the conductive material not being in direct contact with a sidewall surface of the lower portion.

Claims

1. A method of making a semiconductor structure, comprising:

forming a opening partially through a semiconductor substrate, said opening including an upper portion and a lower portion;

forming a first dielectric layer over a sidewall surface of said upper portion, wherein said first dielectric layer not does not overlie a sidewall surface of said lower portion; and

forming a conductive material over a sidewall surface of said first dielectric layer, said conductive material not being in direct contact with a sidewall surface of said lower portion.

2. The method of claim 1, wherein said opening is in a kerf region of said semiconductor substrate.

3. The method of claim 1, wherein said forming said conductive material does not form said conductive material in contact with said sidewall surface of said lower portion.

4. The method of claim 1, wherein said forming said conductive material also forms said conductive material in direct contact with a sidewall surface of said lower portion, said method further comprising removing said conductive material formed in direct contact with said sidewall surface of said lower portion.

5. The method of claim 1, wherein said forming said opening comprises an etching process.

6. The method of claim 5, wherein said etching process comprises a plasma etching process.

7. The method of claim 5, wherein said etching process comprises a Bosch etching process.

8. The method of claim 1, further comprising, after forming said conductive material, removing a portion of said semiconductor substrate so as to separate said semiconductor substrate into a plurality of spaced apart portions.

9. The method of claim 1, wherein said conductive material comprises a metallic material.

10. The method of claim 1, wherein said forming said conductive material comprises depositing said conductive material.

11. The method of claim 10, wherein said depositing said conductive material comprises a physical vapor deposition process.

12. The method of claim 10, wherein said depositing said conductive material comprises a non-conformal deposition process.

13. The method of claim 1, further comprising, before forming said conductive material, forming a second dielectric layer over a top surface of said semiconductor substrate, said conductive material being formed over said second dielectric layer.

14. The method of claim 1, wherein said substrate is a wafer substrate.

15. The method of claim 1, wherein said forming said first dielectric layer forms said first dielectric layer over said upper portion of said opening but not over said lower portion of said opening.

16. The method of claim 1, wherein said forming said first dielectric layer forms said first dielectric layer over said sidewall surface of said upper portion and said sidewall surface of said lower portion, said method further comprising removing said first dielectric layer from said sidewall surface of said lower portion.

17. The method of claim 1, wherein said forming said opening includes forming said upper portion and forming said lower portion after forming said upper portion, said forming said first dielectric layer occurring after forming said upper portion of said opening but before forming said lower portion of said opening.

18. The method of claim 1, wherein said forming said opening includes forming said upper portion and forming said lower portion after forming said upper portion, forming said first dielectric layer occurs after forming said upper portion of said opening and after forming said lower portion of said opening.

19. The method of claim 18, wherein said forming said upper portion and said forming said lower portion is done by the same etching process.