ADAPTIVE OVER-PROVISIONING IN MEMORY SYSTEMS

• US 20140122787A1
• Filed: 01/08/2014
• Published: 05/01/2014
• Est. Priority Date: 07/12/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Shalvi, Ofir, Sommer, Naftali, Kasorla, Yoav
• Granted Patent: US 8,832,531 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Claims

1. An apparatus, comprising:

a cache memory;

a long-term storage unit; and

a controller, wherein the controller is configured to;

receive data from a host for storage;

store the received data in the cache memory;

delete one or more data items from the cache memory responsive to a receiving a trim command from the host; and

increase an over-provisioning ratio dependent upon memory space in the cache memory released by deleting the one or more data items.

2. The apparatus of claim 1, wherein to store the received data in the cache memory, the controller is further configured to store the received data in the long-term storage unit.

3. The apparatus of claim 1, wherein to delete the one or more data items the controller is further configured to determine a number of times each data item stored in the cache memory has been accessed.

4. The apparatus of claim 1, wherein to delete the one or more data items the controller is further configured to determine a duration each data item in the cache memory has been stored.

5. The apparatus of claim 1, wherein the controller is further configured to adaptively modify the over-provisioning ratio.

6. The apparatus of claim 1, wherein the cache memory comprises a plurality of non-volatile memory cells.

7. The apparatus of claim 1, wherein the long-term storage unit includes a magnetic disk.

8. A method for data storage, comprising:

receiving data from a host for storage;

storing the received data in a cache memory;

deleting one or more data items from the cache memory responsive to receiving a trim command from the host; and

increasing an over-provisioning ratio in the cache memory dependent upon memory space in the cache memory released by deleting the one or more data items.

9. The method of claim 8, wherein storing the received data in the cache memory comprises storing the data in a long-term storage unit.

10. The method of claim 8, wherein receiving the trim command from the host comprises sending, by the host, the trim command responsive to a determination that a rate of data storage has decreased.

11. The method of claim 8, wherein receiving the trim command from the host comprises sending, by the host, the trim command responsive to a determination that a rate of data storage is less than a predetermined rate.

12. The method of claim 8, wherein deleting the one or more data items from the cache memory comprises determining a duration each data item in the cache memory has been stored.

13. The method of claim 8, wherein deleting the one or more data items from the cache memory comprises determining a number of times each data item in the cache memory has been accessed.

14. The method of claim 8, wherein the cache memory includes a plurality of non-volatile memory cells.

15. A system, comprising:

a storage unit; and

a host processor configured to send data to the storage unit;

wherein the storage unit includes a cache memory, and wherein the storage unit is configured to;

receive the data sent by the host; and

store the received data in the cache memory;

wherein the host processor is further configured to send a trim command to the storage unit; and

wherein the storage unit is further configured to;

delete one or more data items from the cache memory responsive to receiving the trim command sent by the host; and

increase an over-provisioning ratio in the cache memory dependent upon memory space in the cache memory released by deleting the one or more data items.

16. The system of claim 15, wherein the storage unit further includes a long-term storage unit, and wherein to store the received data in the cache memory, the storage unit is further configured to store the received data in the long-term storage unit.

17. The system of claim 15, wherein to send the trim command to the storage unit, the host processor is further configured to send the trim command responsive to a determination that a rate of data storage to the storage unit has decreased.

18. The system of claim 15, wherein to send the trim command to the storage unit, the host processor is further configured to send the trim command responsive to a determination that a rate of data storage to the storage unit is less than a predetermined rate.

19. The system of claim 15, wherein to delete the one or more data items from the cache memory, the storage unit is further configured to determine a number of times each data item stored in the cache memory has been accessed.

20. The system of claim 15, wherein the cache memory includes a plurality of non-volatile memory cells.