COMPUTER SYSTEM HAVING MAIN MEMORY AND CONTROL METHOD THEREOF

• US 20140122821A1
• Filed: 09/30/2013
• Published: 05/01/2014
• Est. Priority Date: 10/30/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Young-Jin Park
• Inventors: PARK, Young-jin, JUNG, Ilguy
• Granted Patent: US 9,342,257 B2
• Time in Patent Office: Days
• US Class Current: 711/166
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0671 In-line storage system

Abstract

Provided are a computer system and a method of controlling the same. The computer system includes: a central processing unit (CPU) configured to drive an application program; and a main memory configured to provide the CPU with a memory space for driving of the application program and to store a processing result of the CPU. The main memory includes: a nonvolatile memory including a first memory area configured to store data and a second memory area configured to store address information of the data; a memory controller configured to control the nonvolatile memory; and a memory manager configured to read the address information from the second memory area and delete the data stored at the first area according to the read address information, in response to a data delete command from the CPU and a control of the memory controller.

Claims

1. A computer system comprising:

a central processing unit (CPU) configured to drive an application program; and

a main memory configured to provide the CPU with a memory space for driving of the application program and to store a processing result of the CPU,

wherein the main memory comprises;

a nonvolatile memory including a first memory area configured to store data and a second memory area configured to store address information of the stored data;

a memory controller configured to control the nonvolatile memory; and

a memory manager configured to read the address information from the second memory area and to delete the data stored at the first area according to the read address information, in response to a data delete command from the CPU and a control of the memory controller.

2. The computer system of claim 1, wherein the nonvolatile memory is a spin transfer torque magneto resistive random access memory (STT-MRAM), a phase change random access memory (PRAM), or a resistive random access memory (RRAM).

3. The computer system of claim 1, wherein the memory manager is embedded in the memory controller.

4. The computer system of claim 1, wherein the memory manager is configured to read the address information and to delete the address information from the second memory area in response to the data delete command.

5. The computer system of claim 1, further comprising:

a storage configured to store the application program,

wherein the storage is a hard disk drive or a solid state drive.

6. The computer system of claim 5, wherein when the CPU drives the application program, at least a part of the application program is read from the storage and loaded onto the nonvolatile memory.

7. The computer system of claim 1, wherein the data delete command is defined by a data type function being an integer delete function, a string delete function, or a range delete function.

8. The computer system of claim 1, wherein the data delete command is defined by an application program interface function.

9. The computer system of claim 8, wherein the data delete command is executed after a driving of the application program ends.

10. The computer system of claim 1, wherein the address information is stored at a global descriptor table included in the second area.

11. The computer system of claim 1, wherein the data stored at the first memory area is deleted at an idle period of time being an idle state of the CPU.

12. A method of controlling a computer system including a main memory, the method comprising:

receiving a data delete command;

reading address information of data from a first area of the main memory in response to the received data delete command; and

deleting the data stored at a second area of the main memory according to the read address information,

wherein the main memory includes a nonvolatile memory and the nonvolatile memory includes the first area and the second area.

13. The method of claim 12, further comprising:

deleting the address information from the first area after the address information is read.

14. The method of claim 12, wherein the nonvolatile memory is a spin transfer torque magneto resistive random access memory (STT-MRAM), a phase change random access memory (PRAM), or a resistive random access memory (RRAM).

15. The method of claim 12, wherein the deleting the data stored at the second area of the main memory comprises deleting the data stored at the second area at an idle period of time being an idle state of a central processing unit (CPU) in the computer system.

16. A main memory for a computer system, the main memory comprising:

a nonvolatile memory including a first memory area configured to store data and a second memory area configured to store address information of the stored data; and

a memory manager configured to read the address information from the second memory area and to delete the data stored at the first area according to the read address information, in response to a data delete command.

17. The main memory of claim 16, wherein the nonvolatile memory is a spin transfer torque magneto resistive random access memory (STT-MRAM), a phase change random access memory (PRAM), or a resistive random access memory (RRAM).

18. The main memory of claim 16, wherein the memory manager is configured to read the address information and to delete the address information from the second memory area in response to the data delete command.

19. The main memory of claim 16, wherein the nonvolatile memory is configured to provide a memory space for driving an application program and to store a processing result, and is distinct from a storage which stores the application program.

20. The main memory of claim 16, wherein the data stored at the first memory area is deleted at an idle period of time being an idle state of a central processing unit (CPU).