METHODS AND STRUCTURE TO ASSURE DATA INTEGRITY IN A STORAGE DEVICE CACHE IN THE PRESENCE OF INTERMITTENT FAILURES OF CACHE MEMORY SUBSYSTEM

• US 20140122922A1
• Filed: 10/26/2012
• Published: 05/01/2014
• Est. Priority Date: 10/26/2012
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Hunt, Brandon L., McKay, Luke E., Abraham, Moby J., Anupindi, Lakshmana M.
• Granted Patent: US 8,874,973 B2
• Time in Patent Office: Days
• US Class Current: 714/6.11
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training, self-refresh mode of the memory devices is disabled and manual refresh is performed by a processor of the storage device to thereby retain any user data in the memory device.

Claims

1. A method operable in a storage device having a cache memory subsystem, the memory subsystem comprising a DDR memory controller coupling a computational device of the storage device with one or more DDR memory devices, the method comprising:

initializing the storage device where the initialization comprises successfully training the memory controller to interface with the memory devices;

detecting a failure of the memory subsystem;

configuring the memory devices to enable a self-refresh mode responsive to detecting the failure; and

initiating a re-training process between the memory controller and the memory devices responsive to detecting the failure wherein the re-training process comprises the steps of;

configuring the memory devices to disable the self-refresh mode; and

manually refreshing contents of the DDR memory devices by operation of the computational device.

2. The method of claim 1 further comprising:

detecting success of the re-training process; and

responsive to detecting success of the re-training process, restoring error free operation of the storage device.

3. The method of claim 1 further comprising:

detecting failure of the re-training process; and

responsive to detecting failure of the re-training process, performing the steps of;

applying a reset signal to the memory controller without resetting the memory devices; and

repeating the step of initiating the re-training process.

4. The method of claim 1

wherein the step of initiating further comprises applying a reset signal to the memory controller without resetting the memory devices.

5. A method operable in a storage device having a cache memory subsystem, the memory subsystem comprising a DDR memory controller coupling a computational device of the storage device with one or more DDR memory devices, the method operable in response to detecting a failure of the memory subsystem during operation of the storage device following a successful training of the memory controller, the method comprising:

configuring the memory devices to enable a self-refresh mode;

configuring the memory subsystem to de-couple a reset signal applied to the memory controller from a reset signal applied to the memory devices;

applying a reset signal to the memory controller without resetting the memory devices;

determining whether user data is presently stored in the memory devices;

responsive to a determination that no user data is presently stored in the memory devices, performing the steps of;

configuring the memory subsystem to couple the reset signal applied to the memory controller with the reset signal applied to the memory devices;

applying a reset signal to the memory controller and the memory devices; and

re-training the memory controller;

responsive to a determination that user data is presently stored in the memory devices, performing the steps of;

initiating a re-training process between the memory controller and the memory devices; and

during at least a portion of the re-training process, performing the steps of;

configuring the memory devices to disable the self-refresh mode; and

manually refreshing contents of the DDR memory devices by operation of the computational devices.

6. The method of claim 5 further comprising:

detecting success of the re-training;

responsive to detecting success of the re-training, performing the steps of;

configuring the memory devices to enable a self-refresh mode;

configuring the memory subsystem to couple the reset signal applied to the memory controller with the reset signal applied to the memory devices; and

restoring error free operation of the storage device.

7. The method of claim 5 further comprising:

detecting failure of the re-training;

responsive to detecting success of the re-training, performing the steps of;

configuring the memory devices to enable the self-refresh mode;

applying a reset signal to the memory controller without resetting the memory devices; and

repeating the steps of the method.

8. A computer readable medium tangibly embodying programmed instructions which, when executed by a suitable processor perform a method in a storage device having a cache memory subsystem, the memory subsystem comprising a DDR memory controller coupling the processor with one or more DDR memory devices, the method comprising:

initializing the storage device where the initialization comprises successfully training the memory controller to interface with the memory devices;

detecting a failure of the memory subsystem;

configuring the memory devices to enable a self-refresh mode responsive to detecting the failure; and

initiating a re-training process between the memory controller and the memory devices responsive to detecting the failure wherein the re-training process comprises the steps of;

configuring the memory devices to disable the self-refresh mode; and

manually refreshing contents of the DDR memory devices by operation of the computational device.

9. The medium of claim 8 wherein the method further comprises:

detecting success of the re-training process; and

responsive to detecting success of the re-training process, restoring error free operation of the storage device.

10. The medium of claim 8 wherein the method further comprises:

detecting failure of the re-training process; and

responsive to detecting failure of the re-training process, performing the steps of;

applying a reset signal to the memory controller without resetting the memory devices; and

repeating the step of initiating the re-training process.

11. The medium of claim 8

wherein the method step of initiating further comprises applying a reset signal to the memory controller without resetting the memory devices.