IDENTIFICATION OF NON-VOLATILE MEMORY DIE FOR USE IN REMEDIAL ACTION

• US 20140122963A1
• Filed: 10/26/2012
• Published: 05/01/2014
• Est. Priority Date: 10/26/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Motwani, Ravi H., Pangal, Kiran
• Granted Patent: US 9,037,943 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/2927 Decoding strategies
• CPC Class Codes: H03M 13/293 with erasure setting
• CPC Class Codes: H03M 13/2948 Iterative decoding H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding

Abstract

Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile memory for use in remedial action. In various embodiments, a first block may be configured to encode data to be stored in a non-volatile memory as a codeword. In various embodiments, the first block may be configured to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory. In various embodiments, the first block may be configured to generate respective error detection codes for the plurality of die.

Claims

1. An apparatus comprising:

a first block configured to encode data to be stored in a non-volatile memory as a codeword, to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory, and to generate respective error detection codes for the plurality of die; and

a second block coupled to the first block and configured to identify a first die of the plurality of die for use in remedial action, based at least in part on the error detection codes.

2. The apparatus of claim 1, wherein the second block is configured to perform the identification in response to a failed attempt by the first block to decode the codeword.

3. The apparatus of claim 1, further comprising a memory controller, wherein the memory controller comprises the first and second blocks.

4. The apparatus of claim 1, wherein the remedial action comprises an attempt to reconstruct a portion of the codeword read from the first die.

5. The apparatus of claim 1, wherein the remedial action comprises another attempt to decode the codeword in a manner different than the failed attempt.

6. The apparatus of claim 5, wherein the another attempt to decode the codeword includes a designation of bits of the first die as erasures.

7. The apparatus of claim 5, wherein the another attempt to decode the codeword includes a re-read of the codeword from a different demarcation than was used in the failed attempt.

8. The apparatus of claim 1, wherein the identification comprises determination that more sub-portions of a first portion of the codeword stored on the first die include an error than sub-portions of a second portion of the codeword stored on a second die of the plurality of die.

9. The apparatus of claim 8, wherein the determination comprises use of an error detection code generated from the first portion of the codeword.

10. The apparatus of claim 9, wherein the error detection code is used to count sub-portions of the first portion of the codeword that include an error.

11. The apparatus of claim 10, wherein the error detection code comprises a plurality of parity bits.

12. The apparatus of claim 11, wherein the plurality of parity bits are calculated based on respective sub-portions of the first portion of the codeword.

13. The apparatus of claim 10, wherein the plurality of parity bits are XOR results of bits of the respective sub-portions of the first portion.

14. The apparatus of claim 1, wherein the respective error detection codes are stored on respective die.

15. A system comprising:

a storage drive comprising a plurality of die of non-volatile memory; and

a controller having a first block to encode data to be stored in the non-volatile memory as a codeword, to store respective portions of the codeword in a distributed manner across the plurality of die of the non-volatile memory, and to generate respective error detection codes for the plurality of die, and a second block coupled to the first block to identify a first die of the plurality of die for use in remedial action, based at least in part on the error detection codes.

16. The system of claim 15, further comprising a touch screen display.

17. At least one non-transitory computer-readable memory comprising instructions that, responsive to execution of the instructions by a computing device, enable the computing device to operate:

a first block configured to encode data to be stored in a non-volatile memory as a codeword, to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory, and to generate respective error detection codes for the plurality of die; and

a second block configured to identify a first die of the plurality of die for use in remedial action, based at least in part on the error detection codes, responsive to a failed attempt by the first block to decode the codeword.

18. The at least one non-transitory computer-readable medium of claim 17, wherein the remedial action comprises an attempt to reconstruct a portion of the codeword read from the first die.

19. The at least one non-transitory computer-readable medium of claim 17, wherein the remedial action comprises another attempt to decode the codeword in a manner different than the failed attempt, including a designation of bits of the first die as erasures.

20. The at least one non-transitory computer-readable medium of claim 17, wherein the remedial action comprises another attempt to decode the codeword from a different demarcation than was used in the failed attempt.

21. The at least one non-transitory computer-readable medium of claim 17, wherein the identification comprises determination, based on an error detection code generated from a first portion of the codeword stored on the first die, that more sub-portions of the first portion of the codeword include an error than sub-portions of a second portion of the codeword stored on a second die of the plurality of die.

22. The at least one non-transitory computer-readable medium of claim 21, wherein the error detection code is used to count sub-portions of the first portion of the codeword that include an error.

23. The at least one non-transitory computer-readable medium of claim 22, wherein the error detection code comprises a plurality of parity bits calculated based on respective sub-portions of the first portion of the codeword, and wherein the plurality of parity bits are XOR results of bits of the respective sub-portions of the first portion.

24. A computer-implemented method, comprising:

reading, by a controller from a plurality of die of non-volatile memory, respective portions of a codeword stored in a distributed manner across the plurality of die;

identifying, by the controller in response to a failed attempt to decode the codeword, a first die of the plurality of die, based at least in part on respective error detection codes associated with the plurality of die; and

performing, by the controller, remedial action using the first die.

25. The computer-implemented method of claim 24, wherein performing the remedial action comprises attempting to reconstruct a portion of the codeword read from the first die, attempting to decode the codeword in a manner different than the failed attempt, or re-reading of the codeword from a different demarcation than was used in the failed attempt.