LEH Memory Module Architecture Design in the Multi-Level LDPC Coded Iterative System

• US 20140122971A1
• Filed: 10/29/2012
• Published: 05/01/2014
• Est. Priority Date: 10/29/2012
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Li, Zongwang, Chen, Lei, Yang, Shaohua, Yen, Johnson
• Granted Patent: US 9,219,504 B2
• Time in Patent Office: Days
• US Class Current: 714/766
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1137 Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/6331 Error control coding in combination with equalisation
• CPC Class Codes: H03M 13/6505 Memory efficient implementations

Abstract

A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.

Claims

1. A method of decoding a LDPC decoded message, comprising:

interleaving two or more LLR values associated with a LDPC encoded message;

storing the two or more interleaved LLR values in a memory;

sending the two or more interleaved LLR values to a LDPC decoder;

receive two or more extrinsic LLR values from a LDPC decoder; and

store the two or more extrinsic LLR values in the memory.

2. The method of claim 1, wherein sending the two or more interleaved LLR values to a LDPC decoder comprises sending at least 96 interleaved LLR values to the LDPC decoder.

3. The method of claim 1, further comprising:

de-interleaving the two or more extrinsic LLR values;

writing LLR values to a LE queue; and

writing hard decision values to a HD queue,

wherein the two or more extrinsic LLR values comprise at least one LLR value and at least one hard decision value.

4. The method of claim 3, wherein:

writing LLR values to a LE queue comprises writing at least 9 LLR values; and

writing hard decision values to a HD queue comprises writing at least 9 hard decision values.

5. The method of claim 1, wherein the memory comprises a ping-pong memory.

6. The method of claim 1, wherein the memory comprises:

a first data bank 54 bits deep and 168 bits wide; and

a second data bank 54 bits deep and 216 bits wide,

wherein the second data bank is bit enabled.

7. A combined memory apparatus in a LDPC decoder, comprising:

an interleaver;

a memory connected to the interleaver; and

a de-interleaver connected to the memory,

wherein;

the interleaver is configured to interleave two or more LLR values;

the memory is configured to send two or more interleaved LLR values to a LDPC decoder;

the memory is configured to receive two or more interleaved extrinsic LLR values from a LDPC decoder; and

the de-interleaver is configured to de-interleave the two or more extrinsic LLR values.

8. The apparatus of claim 7, wherein the memory is configured to send two or more interleaved LLR values to a LDPC decoder at a rate of at least 96 interleaved LLR values per clock-cycle.

9. The apparatus of claim 7, wherein the de-interleaver is further configured to:

write one or more LLR values to a LE queue; and

write one or more hard decision values to a HD queue.

10. The apparatus of claim 9, wherein the de-interleaver is further configured to:

write the one or more LLR values to a LE queue at a rate of at least 9 LLR values per clock-cycle; and

write one or more hard decision values to a HD queue at a rate of at least 9 hard decision values per clock-cycle.

11. The apparatus of claim 7, wherein the memory comprises a ping-pong memory.

12. The apparatus of claim 7, wherein the memory comprises:

a first data bank 54 bits deep and 168 bits wide; and

a second data bank 54 bits deep and 216 bits wide,

wherein the second data bank is bit enabled.

13. An LDPC decoding apparatus, comprising:

a LEH memory unit comprising;

an interleaver;

a memory connected to the interleaver; and

a de-interleaver connected to the memory;

a LE queue connected to the LEH memory;

a HD queue connected to the LEH memory; and

a LDPC decoder connected to the LEH memory,

wherein;

the interleaver is configured to receive two or more LLR values form the LE queue and interleave the two or more LLR values;

the memory is configured to send two or more interleaved LLR values to the LDPC decoder;

the memory is configured to receive two or more interleaved extrinsic LLR values from the LDPC decoder; and

the de-interleaver is configured to de-interleave the two or more extrinsic LLR values.

14. The apparatus of claim 13, wherein the memory is configured to send two or more interleaved LLR values to the LDPC decoder at a rate of at least 96 interleaved LLR values per clock-cycle.

15. The apparatus of claim 13, wherein the de-interleaver is further configured to:

write one or more LLR values to the LE queue; and

write one or more hard decision values to the HD queue.

16. The apparatus of claim 15, wherein the de-interleaver is further configured to:

write the one or more LLR values to the LE queue at a rate of at least 9 LLR values per clock-cycle; and

write one or more hard decision values to the HD queue at a rate of at least 9 hard decision values per clock-cycle.

17. The apparatus of claim 13, wherein the memory comprises a ping-pong memory.

18. The apparatus of claim 17, wherein the memory comprises:

a plurality of first data banks having a first bit width; and

a plurality of second bit-enabled data banks having a second width.

19. The apparatus of claim 13, wherein the memory comprises:

a first data bank 54 bits deep and 168 bits wide; and

a second data bank 54 bits deep and 216 bits wide,

wherein the second data bank is bit enabled.

20. The apparatus of claim 13, wherein the LDPC decoder is a multi-layer decoder.