Radiation-Hardened Power Semiconductor Devices and Methods of Forming Them

• US 20140124851A1
• Filed: 11/08/2012
• Published: 05/08/2014
• Est. Priority Date: 11/08/2012
• Status: Active Application

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Gamerith, Stefan, Schmitt, Markus, Kaindl, Winfried, Slkner, Gerald
• Granted Patent: US 10,256,325 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.

Claims

1. A method of forming a power semiconductor device, comprising:

providing a semiconductor substrate;

forming an epitaxial layer on the semiconductor substrate, the epitaxial layer comprising a body region, a source region, and a drift region;

forming a dielectric layer on the epitaxial layer, wherein the dielectric layer is formed thicker above the drift region of the epitaxial layer than above at least part of the body region and wherein the dielectric layer is formed at a temperature less than 950°

C.; and

forming a gate electrode on the dielectric layer at least above the body region.

2. The method according to claim 1, wherein forming the dielectric layer comprises:

forming the dielectric layer thicker in a first part above the body region than in a second part above the body region.

3. The method according to claim 1, wherein forming the dielectric layer comprises:

forming a cap oxide layer;

and forming a gate oxide layer above the cap oxide layer.

4. The method according to claim 3, wherein the cap oxide layer is formed by local oxidation of silicon (LOCOS).

5. The method according to claim 1, wherein forming the epitaxial layer comprises:

forming a superjunction structure in the epitaxial layer, wherein

(a) an upper superjunction zone of the superjunction structure below the body region is formed with a higher first-type doping than a lower superjunction zone of the superjunction structure below the upper superjunction zone, or

(b) an upper drift zone of the drift region laterally adjacent to the upper superjunction zone is formed with a higher second-type doping than a lower drift zone below the upper drift zone, or

(c) the upper superjunction zone is formed with a higher first-type doping than the lower superjunction zone and the upper drift zone is formed with a higher second-type doping than the lower drift zone;

wherein the difference between the first-type net doping dose of the upper superjunction zone and the second-type net doping dose of the upper drift zone is larger than the difference between the first-type net doping dose of the lower superjunction zone and the second-type net doping dose of the lower drift zone.

6. The method according to claim 5, wherein forming the upper superjunction zone comprises implanting a first dose of a dopant, the first dose being between 1×

10¹¹ and 1×

10¹⁵ cm<sup>−

2</sup> of the first-type dopant, and wherein forming the upper drift zone comprises implanting a second dose of a dopant, the second dose being between 1×

10¹¹ and 1×

10¹⁵ cm<sup>−

2</sup> of a second-type dopant.

7. The method according to claim 5, wherein forming the epitaxial layer comprises:

forming a second-type doped uppermost drift zone above the upper drift zone and laterally adjacent to the body region, wherein the second-type doping of the uppermost drift zone is higher than the second-type doping of the at least one lower drift zone.

8. The method according to claim 1, wherein forming the epitaxial layer comprises:

forming a buffer layer directly above the semiconductor substrate, wherein the buffer layer is formed with a second-type doping that decreases in a direction from the semiconductor substrate to the epitaxial layer.

9. The method according to claim 8, wherein forming the buffer layer comprises:

(i) decreasing the doping concentration while forming the buffer layer to form a buffer layer with graded doping, wherein a first zone of the buffer layer with graded doping closest to the epitaxial layer has a mean doping less than or equal to 4×

10¹⁵ cm<sup>−

3</sup>;

or

(ii) forming a first sub-layer and at least one second sub-layer with different doping, wherein the first sub-layer, which is closest to the epitaxial layer, has a doping less than or equal to 4×

10¹⁵ cm<sup>−

3</sup>.

10. The method according to claim 9, wherein a thickness of the first sub-layer or of the first zone is at least 8 μ

m, and wherein a thickness of the buffer layer is at least 12 μ

m.

11. The method according to claim 1, wherein the power semiconductor device is a power MOSFET or insulated-gate bipolar transistor.

12. A method of forming a power semiconductor device, comprising:

providing a semiconductor substrate; and

forming an epitaxial layer above the semiconductor substrate, the epitaxial layer comprising a body region, a drift region, and a superjunction structure,

wherein

(a) an upper superjunction zone of the superjunction structure arranged below the body region has a higher first-type doping than a lower superjunction zone of the superjunction structure below the upper superjunction zone, or

(b) an upper drift zone of the drift region laterally adjacent to the upper superjunction zone has a higher second-type doping than a lower drift zone below the upper drift zone, or

(c) the upper superjunction zone has a higher first-type doping than the lower superjunction zone and the upper drift zone has a higher second-type doping than the lower drift zone;

wherein the difference between the first-type net doping dose of the upper superjunction zone and the second-type net doping dose of the upper drift zone is larger than the difference between the first-type net doping dose of the lower superjunction zone and the second-type net doping dose of the lower drift zone.

13. A method of forming a power semiconductor device, comprising:

providing a semiconductor substrate; and

forming an epitaxial layer on the semiconductor substrate, the epitaxial layer comprising a buffer layer arranged directly above the semiconductor substrate, wherein the buffer layer has a second-type doping that decreases in a direction from the semiconductor substrate to the epitaxial layer.

14. A power semiconductor device, comprising:

a semiconductor substrate;

an epitaxial layer above the semiconductor substrate, the epitaxial layer comprising a body region, a source region forming a pn-junction with the body region;

a dielectric layer above the epitaxial layer; and

a gate electrode above the dielectric layer for controlling an inversion channel in the body region between the source region and a drift region, at least the source region being connected to a source electrode, and the substrate being connected to a drain electrode,

wherein the dielectric layer is thicker above the drift region than above at least part of the body region and wherein the dielectric layer has a specific micro-structure as obtained by forming the dielectric layer with a low-temperature process at a temperature less than 950°

C.

15. The semiconductor device of claim 14, wherein the ratio of a thickness of the dielectric layer and of a thickness of the gate electrode varies along the length of the gate electrode.

16. The semiconductor device of claim 14, wherein the dielectric layer is thicker above the drift region than above at least part of the body region.

17. The semiconductor device of claim 14, wherein the dielectric layer includes a cap oxide layer at least above the drift region, and a gate oxide layer above both the drift region and the body region.

18. The semiconductor device of claim 14, wherein the dielectric layer includes a cap oxide layer above the drift region and above a part of the body region, and a gate oxide layer above both the drift region and the body region.

19. A power semiconductor device, comprising:

a semiconductor substrate;

an epitaxial layer above the semiconductor substrate, the epitaxial layer comprising;

a first-type doped superjunction structure,

a body region connected to the superjunction structure,

a source region forming a pn-junction with the body region, and

a second-type doped drift region;

a dielectric layer above the epitaxial layer; and

a gate electrode above the dielectric layer for controlling an inversion channel in the body region between the source region and the drift region, at least the source region being connected to a source electrode, and the substrate being connected to a drain electrode,

wherein

(a) an upper superjunction zone of the superjunction structure below the body region contains a higher first-type doping than a lower superjunction zone of the superjunction structure below the upper superjunction zone, or

(b) an upper drift zone of the drift region laterally adjacent to the upper superjunction zone contains a higher second-type doping than a lower drift zone of the drift region below the upper drift zone, or

(c) the upper superjunction zone contains a higher first-type doping than the lower superjunction zone and the upper drift zone contains a higher second-type doping than the lower drift zone;

and wherein the difference between the first-type net doping dose of the upper superjunction zone and the second-type net doping dose of the upper drift zone is larger than the difference between the first-type net doping dose of the lower superjunction zone and the second-type net doping dose of the lower drift zone.

20. The power semiconductor device of claim 19, wherein the doping of the upper superjunction zone is at least 20% higher than the doping of the lower superjunction zone, and wherein the doping of the upper drift zone is at least 20% higher than the doping of the lower drift zone.

21. The power semiconductor device of claim 19, wherein the difference between the first-type net doping dose of the upper superjunction zone and the second-type net doping dose of the upper drift zone is at least 50% larger than the difference between the first-type net doping dose of the lower superjunction zone and the second-type net doping dose of the lower drift zone.

22. The power semiconductor device of claim 19, wherein an uppermost drift zone above the upper drift zone and laterally adjacent to the body region has a second-type doping that is higher than the second-type doping of the lower drift zone.

23. A power semiconductor device, comprising:

a semiconductor substrate;

an epitaxial layer above the semiconductor substrate, the epitaxial layer comprising a body region, a source region forming a pn-junction with the body region, a drift region, and a buffer layer directly above the semiconductor substrate;

a dielectric layer above the epitaxial layer;

a gate electrode above the dielectric layer for controlling an inversion channel in the body region between the source region and the drift region, at least the source region being connected to a source electrode, and the substrate being connected to a drain electrode;

wherein the buffer layer has a second-type doping that decreases in a direction from the semiconductor substrate to the epitaxial layer.

24. The power semiconductor device of claim 23, wherein the buffer layer is a buffer layer with graded doping and a first zone of the buffer layer with graded doping most remote from the semiconductor substrate has a mean doping less than or equal to 4×

10¹⁵ cm<sup>−

3</sup>, or wherein the buffer layer is a buffer layer including a first sub-layer and at least one second sub-layer with different doping

and the first sub-layer, which is most remote from the semiconductor substrate, has a doping less than or equal to 4×

10¹⁵ cm<sup>−

3</sup>.

25. The power semiconductor device of claim 24, wherein a thickness of the first sub-layer or of the first zone is at least 8 μ

m, and wherein a thickness of the buffer layer is at least 12 μ

m.