POWER MANAGEMENT MULTI-CHIP MODULE WITH SEPARATE HIGH-SIDE DRIVER INTEGRATED CIRCUIT DIE

• US 20140125266A1
• Filed: 11/05/2012
• Published: 05/08/2014
• Est. Priority Date: 11/05/2012
• Status: Active Grant

• Current Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Original Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Inventors: Huynh, Steven, Hsu, Tsing
• Granted Patent: US 9,000,702 B2
• Time in Patent Office: Days
• US Class Current: 318/400.27
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 7/5387 in a bridge configuration
• CPC Class Codes: H02P 6/085 in a bridge configuration
• CPC Class Codes: H02P 6/14 Electronic commutators
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice. The disable signal is generated without execution of processor instructions.

Claims

1. A packaged multi-chip module, comprising:

a first set of three package terminals A, B and C;

a second set of three package terminals D, E and F that is separated from the first set by at least one millimeter;

a low-side driver output package terminal G;

at least two dice that include a processor, a timer, a low-side driver, a first high-side driver and a second high-side driver, wherein a first of the two dice includes the processor and the timer, wherein a second of the two dice includes the first and second high-side drivers, wherein the first high-side driver is controllable by the processor and the timer, wherein three terminals of the first high-side driver are coupled to the first set of three package terminals A, B and C, wherein three terminals of the second high-side driver are coupled to the second set of three package terminals D, E and F, and wherein the low-side driver is coupled to the low-side driver output package terminal G; and

a die paddle, wherein each of the at least two dice has a substrate, wherein the substrate of the second of the at least two dice is a P-type substrate, and wherein the substrate of each of the at least two dice is equipotential to the die paddle.

2. The packaged multi-chip module of claim 1, wherein a first set of voltages is present on the first set of three package terminals A, B and C during operation of the packaged multi-chip module, wherein each voltage of the first set of voltages is within twenty volts of each of the other voltages of the first set of voltages, wherein a second set of voltages is present on the second set of three package terminals D, E and F during the operation of the packaged multi-chip module, wherein each voltage of the second set of voltages is within twenty volts of each of the other voltages of the second set of voltages, and wherein a difference between one of the first set of voltages and one of the second set of voltages is at least eighty volts.

3. The packaged multi-chip module of claim 1, wherein the first of the two dice includes Complementary Metal-Oxide-Semiconductor (CMOS) circuitry and includes no Double-diffused Metal-Oxide-Semiconductor (DMOS) circuitry capable of operating above one-hundred volts, and the second of the two dice includes DMOS circuitry capable of operating above one-hundred volts.

4. The packaged multi-chip module of claim 1, wherein the first of the two dice includes the low-side driver, wherein the low-side driver drives a gate of a low-side transistor external to the packaged multi-chip module, wherein the packaged multi-chip module includes a pulse-width controller, wherein the pulse-width controller is part of a switching power supply that generates a supply voltage, and wherein the supply voltage is supplied to the low-side driver.

5. The packaged multi-chip module of claim 1, wherein the packaged multi-chip module includes a pulse-width controller, wherein the pulse-width controller is part of a switching power supply that generates a supply voltage, wherein the first high-side driver of the second of the two dice is supplied by the supply voltage and generates a set of voltages, and wherein one of the set of voltages is supplied to a gate of a high-side transistor.

6. The packaged multi-chip module of claim 1, wherein the packaged multi-chip module includes a voltage detect package terminal, wherein the first of the two dice further includes a protection control circuit, wherein the protection control circuit supplies a digital logic disable signal to the second of the two dice via a disable terminal of the first of the two dice, and wherein a signal propagation delay from the voltage detect package terminal to the disable terminal is not affected by an execution time of any instruction executed by the processor.

7. The packaged multi-chip module of claim 6, wherein no structure capable of executing instructions causes the digital logic disable signal to switch.

8. The packaged multi-chip module of claim 1, wherein the packaged multi-chip module includes more than one high-side driver, and wherein the second of the two dice does not include any low-side drivers.

9. The packaged multi-chip module of claim 1, further comprising:

a third set of three package terminals, wherein the second of the two dice further includes a third high-side driver, wherein three terminals of the third high-side driver are coupled to the third set of three package terminals, and wherein the first, second and third set of three package terminals drive a three-phase electric motor.

10. A method, comprising:

(a) coupling a first die to a second die thereby forming a packaged multi-chip module, wherein the first die includes a processor and a timer, wherein the second die includes a first high-side driver and a second high-side driver, wherein the first high-side driver is controllable by the processor and the timer, wherein the packaged multi-chip module includes a first set of three package terminals A, B and C and a second set of three package terminals D, E and F, wherein the second set is separated from the first set by at least one millimeter, wherein three terminals of the first high-side driver are coupled to the first set of three package terminals A, B and C, wherein three terminals of the second high-side driver are coupled to the second set of three package terminals D, E and F, and wherein a substrate of each of the first die and second die is equipotential to a die paddle of the packaged multi-chip module.

11. The method of claim 10, wherein a first set of voltages is present on the first set of three package terminals A, B and C during operation of the packaged multi-chip module, wherein each voltage of the first set of voltages is within twenty volts of each of the other voltages of the first set of voltages, wherein a second set of voltages is also present on the second set of three package terminals D, E and F during the operation of the packaged multi-chip module, wherein each voltage of the second set of voltages is within twenty volts of each of the other voltages of the second set of voltages, and wherein a difference between one of the first set of voltages and one of the second set of voltages is at least eighty volts.

12. The method of claim 10, wherein the first die includes Complementary Metal-Oxide-Semiconductor (CMOS) circuitry and includes no Double-diffused Metal-Oxide-Semiconductor (DMOS) circuitry capable of operating above one-hundred volts, and wherein the second die has a P-type substrate and includes DMOS circuitry capable of operating above one-hundred volts.

13. The method of claim 10, wherein the first die includes a low-side driver, wherein the low-side driver drives a gate of a low-side transistor external to the packaged multi-chip module, wherein the packaged multi-chip module includes a pulse-width controller, wherein the pulse-width controller is part of a switching power supply that generates a supply voltage, and wherein the supply voltage is supplied to the low-side driver.

14. The method of claim 10, wherein the packaged multi-chip module includes a pulse-width controller, wherein the pulse-width controller is part of a switching power supply that generates a supply voltage, wherein the first high-side driver of the second die is supplied by the supply voltage and generates a set of voltages, and wherein one of the set of voltages is supplied to a gate of the high-side transistor.

15. The method of claim 10, further comprising the step of:

(b) providing a connection from the first die to the second die that carries a digital logic enable signal, wherein the packaged multi-chip module includes a voltage detect package terminal, wherein the first die further includes a protection control circuit and a disable terminal, wherein the connection extends from the disable terminal to a terminal of the second die, wherein the protection control circuit supplies the digital logic disable signal to the second die via the connection, and wherein a signal propagation delay from the voltage detect package terminal to the disable terminal is not affected by an execution time of any instruction executed by the processor.

16. The method of claim 15, wherein no structure capable of executing instructions causes the digital logic disable signal to switch.

17. The method of claim 10, wherein the packaged multi-chip module includes more than one high-side driver, and wherein the second die does not include any low-side drivers.

18. The method of claim 10, further comprising the step of:

(b) using the packaged multi-chip module to drive a three-phase electric motor.

19. A packaged multi-chip module, comprising:

a first die that includes a processor and a timer; and

means for supplying and controlling at least two sets of high-side driver voltages, wherein a first of the two sets of high-side driver voltages is supplied onto a first set of three package terminals A, B and C of the packaged multi-chip module, wherein a second of the two sets of high-side driver voltages is supplied onto a second set of three package terminals D, E and F of the packaged multi-chip module, and wherein the second set of three package terminals D, E and F is separated from the first set of three package terminals A, B and C by at least one millimeter.

20. The packaged multi-chip module of claim 19, wherein each voltage of the first set of high-side driver voltages is within twenty volts of each of the other voltages of the first set, wherein each voltage of the second set of high-side driver voltages is within twenty volts of each of the other voltages of the second set, and wherein a difference between one of the high-side driver voltages of the first set and one of the high-side driver voltages of the second set is at least eighty volts.

21. The packaged multi-chip module of claim 19, wherein the means is a second die that includes a first high-side driver and a second high-side driver, wherein the first high-side driver generates the first of the two sets of high-side driver voltages, wherein the second high-side driver generates the second of the two sets of high-side driver voltages, wherein the first die includes Complementary Metal-Oxide-Semiconductor (CMOS) circuitry and includes no Double-diffused Metal-Oxide-Semiconductor (DMOS) circuitry capable of operating above one-hundred volts, and wherein the second die includes DMOS circuitry capable of operating above one-hundred volts.

22. A system, comprising:

a multi-chip module comprising;

a low-side driver output package terminal G;

a first die that has a processor, a timer, a pulse width modulator circuit and at least one low-side driver coupled to the low-side driver output package terminal G;

a first set of three package terminals A, B and C;

a second set of three package terminals D, E and F that is separated from the first set by at least one millimeter; and

a second die having a first high-side driver and a second high-side driver, wherein three terminals of the first high-side driver are coupled to the first set of three package terminals A, B and C, and wherein three terminals of the second high-side driver are coupled to the second set of three package terminals D, E and F;

a high-side transistor, wherein a gate of the high-side transistor is coupled to one of the set of three package terminals A, B and C;

a low-side transistor, wherein the low-side driver output package terminal G is coupled to a gate of the low-side transistor; and

a three-phase electric motor, wherein a source of the high-side transistor is coupled to a winding terminal of the motor, and wherein a drain of the low-side transistor is coupled to the winding terminal of the motor.