METHOD AND APPARATUS REDUCED SWITCH-ON RATE LOW DROPOUT REGULATOR (LDO) BIAS AND COMPENSATION

• US 20140125300A1
• Filed: 03/07/2013
• Published: 05/08/2014
• Est. Priority Date: 11/06/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Price, Burt L., Kolla, Yeshwant Nagaraj, Shah, Dhaval R.
• Granted Patent: US 9,235,225 B2
• Time in Patent Office: Days
• US Class Current: 323/281
• CPC Class Codes: G05F 1/468 characterised by reference voltage circuitry, e.g. soft start, remote shutdown
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A switchable bias current biases, in an operational state, a differential amplifier with a full-slew bias current. A system on/off signal transitions from an operational state to a power-down state. The transition disables the differential amplifier and switches the switchable bias current to a reduced slew bias current. The system on/off signal transitions from the power-down state to the operational state, the differential amplifier is enabled, and the switchable bias current is delayed, by a reduced slew duration, from switching to the full-slew bias current. The enabled differential amplifier slews toward a reference voltage at a reduced slew rate caused by the reduced slew bias current. The switchable bias current, after the reduced slew duration, switches to the full-slew bias current. Optionally, a regulated pass gate is disabled in response to the system on/off signal transitioning from the operational state to the power-down state.

Claims

1. A reduced switch-on slew low dropout (LDO) regulator comprising:

a pass gate controllably coupling, in response to a pass gate control signal, a voltage rail to a regulator output; and

a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state.

2. The reduced switch-on slew LDO regulator of claim 1, further comprising:

a pass gate disabling circuit configured to selectively over-ride the pass gate control signal and switch the pass gate OFF.

3. The reduced switch-on slew regulator of claim 2, wherein the controllable slew differential amplifier includes a switchable tail current source that is switchable between sourcing a slew-limiting bias current and sourcing a full-slew bias current, and is configured to generate the pass gate control signal at the full-slew rate with the full-slew bias current, and at the reduced slew rate with the slew-limiting bias current.

4. The reduced switch-on slew LDO regulator of claim 3, wherein the switchable tail current source includes a switchable full-slew bias current source configured to source the full-slew bias current when ON, in parallel with a slew-limiting bias current source configured to source the slew-limiting bias current.

5. The reduced switch-on slew LDO regulator of claim 4, further comprising a tail current control circuit configured to switch OFF the switchable full-slew bias current source in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay DIN after an OFF-to-ON transition of ST_OFF, to switch ON the switchable full-slew bias current source.

6. The reduced switch-on slew LDO regulator of claim 3, further comprising a tail current control circuit configured to switch the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay DLY after an OFF-to-ON transition of ST_OFF, to switch the switchable tail current source from the slew-limiting bias current to the full-slew bias current.

7. The reduced switch-on slew LDO regulator of claim 6, wherein the controllable slew differential amplifier is configured to slew, in response to the OFF-to-ON transition of ST_ON/OFF, from an initial zero voltage to approximately Vref, at a slew rate stewing from the initial zero voltage to approximately Vref in a time duration approximately equal to DLY.

8. The reduced switch-on slew LDO regulator of claim 7, wherein the tail current control circuit includes a delay capacitor, and a charging circuit configured to charge the delay capacitor, in response to the OFF-to-ON transition of ST_ON/OFF, from a zero voltage to a tail current source mode switch threshold, in a charging time having a duration approximately equal to DIN.

9. The reduced switch-on slew LDO regulator of claim 8, wherein the charging circuit includes a trigger switch coupled to a charging current source.

10. The reduced switch-on slew LDO regulator of claim 2, further comprising:

a pass gate control line carrying the pass gate control signal to a control gate of the pass gate, wherein the pass gate disabling circuit comprises a two-position switch, the two-position switch having a disabling position and an operational position, wherein the disabling position provides a short of the control gate to a voltage disabling the pass gate, and the operational position does not provide the short of the control gate, wherein the two-position switch is configured to switch between the disabling position and the operational position based on an ON-OFF state of ST_OFF/ON.

11. The reduced switch-on slew LDO regulator of claim 10, further comprising a feedback element that is coupled to the regulator output and to an input of the controllable slew differential amplifier to provide said feedback, and a compensation network coupling the pass gate control line to the feedback element, the compensation network having a compensation capacitor and a compensation resistor, and wherein the pass gate disabling circuit is further configured to charge the compensation capacitor when the two position switch is in the disabling position.

12. The reduced switch-on slew LDO regulator of claim 11, wherein the pass gate disabling circuit is further configured to allow the compensation capacitor to discharge the pass gate control line, to a voltage at which the pass gate is operational, in response to switching the two-position switch from the disabling position to the operational position.

13. The reduced switch-on slew LDO regulator of claim 12, wherein a rate of the reduced slew rate is based, at least in part, on at least one of a capacitance of the compensation capacitor or a resistance of the compensation resistor, or both.

14. The reduced switch-on slew LDO regulator of claim 13, wherein the controllable slew differential amplifier includes a switchable, tail current source switchable between sourcing a slew-limiting bias current and a full-slew bias current,

wherein the controllable slew differential amplifier is configured to generate the pass gate control signal at the full-slew rate with the full-slew bias current, and at the reduced slew rate with the slew-limiting bias current, and

wherein a rate of the reduced slew rate is further based, at least in part, on the slew-limiting bias current and at least one of a capacitance of the compensation capacitor or a resistance of the compensation resistor, or both.

15. The reduced switch-on slew LDO regulator of claim 14, further comprising a tail current control circuit configured to switch the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay DLY after an OFF-to-ON transition of ST_OFF, to switch the switchable tail current source from the slew-limiting bias current to the full-slew bias current.

16. The reduced switch-on slew LDO regulator of claim 15, wherein the controllable slew differential amplifier is configured to slew, in response to the OFF-to-ON transition of ST_ON/OFF, from an initial zero voltage to approximately Vref, at a slew rate stewing from the initial zero voltage to approximately Vref in a time duration approximately equal to DLY.

17. The reduced switch-on slew LDO regulator of claim 16, wherein the tail current control circuit includes a capacitor and a charging current source configured to charge the capacitor from a zero voltage to a tail current source mode switch threshold in a charging time duration approximately equal to DLY.

18. A method for reduced switch-on slew low dropout (LDO) regulating with a pass gate controlled by a differential amplifier having differential inputs, and a transistor controlled by one of the differential inputs, comprising:

biasing the transistor with a bias current, the bias current being a full-slew bias current;

providing to the differential inputs a reference voltage and a feedback of an output of the pass gate;

in response to an ON-to-OFF transition of a system on/off signal (ST_ON/OFF), disabling the feedback and switching the bias current to a slew-limiting bias current, lower than a full-slew bias current;

in response to an OFF-to-ON transition of ST_ON/OFF, enabling the feedback to the differential amplifier; and

at a time delayed from said OFF-to-ON transition by a reduced slew duration, switching the bias current to biasing to the full-slew bias current.

19. The method of claim 18, wherein the switching the biasing to bias the transistor with the full-slew bias current includes commencing, in response to said OFF-to-ON transition, a charging of a delay capacitor and, in response to the delay capacitor reaching a given threshold voltage level, performing the switching the biasing to bias the transistor with the full-slew bias current.

20. The method of claim 18, wherein biasing the transistor with the full-slew bias current comprises:

generating, in response to the ON state of ST_ON/OFF, a biasing current source control signal at an ON level, and

controlling a current source coupled to the transistor based on the biasing current source control signal at the ON level.

21. The method of claim 20, wherein switching the biasing to bias the transistor with the slew-limiting bias current comprises:

generating, in response to the ON-to-OFF transition of ST_ON/OFF, the biasing current source control signal at an OFF level; and

controlling the current source coupled to the transistor based on the biasing current source control signal at the ON level.

22. The method of claim 21, wherein the switching the biasing to bias the transistor with the full-slew bias current includes commencing, in response to the OFF-to-ON transition, a charging of a delay capacitor and, in response to the delay capacitor reaching a given voltage level, performing the switching the biasing to bias the transistor with the full-slew bias current.

23. A reduced switch-on slew low dropout (LDO) regulator comprising:

a differential amplifier having difference inputs, an output, and a transistor having a gate coupled to one of the difference inputs;

a pass gate controlled by the output of the differential amplifier, the pass gate having a pass gate input for coupling to a power rail, and a pass gate output;

means for receiving a system ON/OFF signal (ST_ON/OFF) and,

in response to an OFF-to-ON transition of ST_ON/OFF, establishing a feedback from the pass gate output to one of the difference inputs and biasing the transistor with a full-slew bias current, and

in response to an ON-to-OFF transition of ST_ON/OFF, disabling the feedback and switching the biasing of the transistor to a slew-limiting bias current.