DUTY CYCLE CORRECTION APPARATUS

• US 20140125391A1
• Filed: 06/25/2012
• Published: 05/08/2014
• Est. Priority Date: 06/24/2011
• Status: Abandoned Application

• Current Assignee: LSIS Co. Ltd. (LS Corporation)
• Original Assignee: LSIS Co. Ltd. (LS Corporation)
• Inventors: Seon, Jong Kug
• Application Number:
  US14/127,876
• Publication Number:
  US 20140125391A1
• Time in Patent Office: Days
• US Class Current: 327/175
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

Disclosed is a duty cycle correction apparatus. The apparatus of the present invention adjusts signal widths of an input signal, averages the widths of the signal, and inverts the signal, then averages the widths of the inverted signal, compares the two averaged signals, and outputs the difference between the two averaged signals.

Claims

1. An apparatus for correcting duty cycle, the apparatus configured to correct a duty ratio of an input signal, the apparatus comprising:

an alert clock configured to adjust a signal width of the input signal;

a first equalization unit configured to equalize a width of an output signal of the alert clock;

an inverter configured to reverse the output signal of the alert clock;

a second equalization unit configured to equalize a width of an output signal of the inverter; and

a comparator configured to compare the output signals of the first and second equalization units, and output a difference between the output signals of the first and second equalization units.

2. The apparatus of claim 1, wherein the alert clock is configured to adjust the width of the input signal using an output of the comparator.

3. The apparatus of claim 1, further comprising:

a selector configured to select a ratio of the output signals of the first and second equalization units to allow the comparator to output the difference in response to the ratio.

4. The apparatus of claim 1, further comprising:

a first buffer configured to temporarily store an output of the alert clock and output the output of the alert clock to the first equalization unit.

5. The apparatus of claim 4, wherein the inverter is configured to reverse an output of the first buffer.

6. The apparatus of claim 4, further comprising:

a second buffer configured to temporarily store and output an output of the first buffer.

7. The apparatus of claim 2, wherein the output of the comparator is inputted to the alert clock until the output of the comparator substantially becomes zero, when a duty ratio of the output of the alert clock matches that of the output of the inverter.

8. The apparatus of claim 2, wherein the alert clock comprises:

a controller configured to control the width of input signal in response to the output of the comparator, and

a first switch configured to turn on or off operation of the controller.

9. The apparatus of claim 2, wherein each of the first and second equalization units comprises:

a current source configured to supply a current,

a second switch configured to switch the current supplied from the current source in response to high and low level of an inputted voltage, and

an LPF (Low Pass Filter) configured to equalize a width of the voltage inputted using the current of the current source in response to the switching of the second switch and to output the equalized width.

10. The apparatus of claim 9, wherein the LPF includes a capacitor.