SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS

• US 20140127906A1
• Filed: 11/07/2012
• Published: 05/08/2014
• Est. Priority Date: 11/07/2012
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cabral, Cyril Jr., Fletcher, Benjamin L., Fuller, Nicholas C.M., Joseph, Eric A., Miyazoe, Hiroyuki
• Application Number:
  US13/671,166
• Publication Number:
  US 20140127906A1
• Time in Patent Office: Days
• US Class Current: 438/694
• CPC Class Codes: H01L 21/32131 by physical means only
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Fabricating conductive lines in an integrated circuit includes providing a conductive metal in a multi-layer structure, performing a first sputter etch of the conductive metal using methanol plasma, and performing a second sputter etch of the conductive metal using a second plasma, wherein a portion of the conductive metal that remains after the second sputter etch forms the conductive lines. Alternatively, fabricating conductive lines includes providing a conductive metal as an intermediate layer in a multi-layer structure, etching the multi-layer structure to expose the conductive metal, performing a first etch of the conductive metal using methanol plasma, performing a second sputter etch of the conductive metal using a second plasma, wherein a portion of the conductive metal that remains after the second sputter etch forms the conductive lines, forming a liner that surrounds the conductive lines, and depositing a dielectric layer on the multi-layer structure.

Claims

1. A method for fabricating one or more conductive lines in an integrated circuit, the method comprising:

providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer;

performing a first sputter etch of the layer of conductive metal using a methanol plasma; and

performing a second sputter etch of the layer of conductive metal using a second plasma, wherein a portion of the layer of conductive metal that remains after the second sputter etch forms the one or more conductive lines.

2. The method of claim 1, wherein the second plasma comprises helium plasma.

3. The method of claim 1, wherein the layer of conductive metal comprises gold.

4. The method of claim 1, wherein the layer of conductive metal comprises nickel.

5. The method of claim 1, wherein the layer of conductive metal comprises cobalt.

6. The method of claim 1, wherein the multi-layer structure comprises:

a first dielectric layer formed on the wafer;

a first liner layer formed on the first dielectric layer;

the layer of conductive metal formed on the first liner layer;

a first hard mask layer formed on the layer of conductive metal;

a second hard mask layer formed on the first hard mask layer;

an organic underlayer formed on the second hard mask layer; and

a photoresist layer formed on the organic underlayer.

7. The method of claim 6, wherein the first hard mask layer comprises tantalum.

8. The method of claim 6, wherein the first hard mask layer comprises titanium.

9. The method of claim 6, wherein the first liner layer comprises titanium nitride.

10. The method of claim 6, wherein the first liner layer comprises tantalum nitride.

11. The method of claim 6, further comprising, prior to the sputter etching:

transferring a pattern from the organic underlayer and the second hard mask layer to the first hard mask layer.

12. The method of claim 11, wherein the pattern is formed in the organic underlayer and the second hard mask layer using a photolithography technique.

13. The method of claim 11, wherein the transferring comprises:

developing the photoresist layer;

etching the second hard mask layer down to the first hard mask layer, such that only a portion of the second hard mask layer residing directly beneath the organic underlayer remains and becomes a patterned second hard mask layer;

removing the organic underlayer and the photoresist layer;

exposing the patterned second hard mask layer; and

etching the first hard mask layer down to the layer of conductive metal, such that only a portion of the first hard mask layer residing directly beneath the patterned second hard mask layer metal remains and becomes a patterned first hard mask layer.

14. The method of claim 13, wherein the first sputter etch etches the layer of conductive metal a portion of the way down to the first liner layer, and the second sputter etch etches the layer of conductive metal a remainder of the way down to the first liner layer, such that a remaining portion of the layer of conductive metal comprises a pyramidal profile residing directly beneath the patterned first hard mask layer.

15. The method of claim 14, further comprising, subsequent to performing the second sputter etch:

forming a liner that surrounds the one or more conductive lines; and

depositing a second dielectric layer on the multi-layer structure.

16. The method of claim 15, wherein the forming comprises:

etching the first liner layer down to the first dielectric layer, such that only a portion of the first liner layer residing directly beneath the layer of conductive metal remains and lines a base of one or more trenches;

depositing a second liner layer on the multi-layer structure; and

etching the second liner layer such that a remaining portion of the second liner layer lines sidewalls of the one or more trenches.

17. The method of claim 15, wherein the second dielectric layer comprises a low-k dielectric material.

18. The method of claim 1, wherein each of the one or more conductive lines has a width of less than approximately forty nanometers.

19. The method of claim 1, wherein the first sputter etch is performed at a first etch rate, and the second sputter etch is performed at a second etch rate that is lower than the first etch rate.

20. A method for fabricating one or more conductive lines in an integrated circuit, the method comprising:

providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, wherein the layer of conductive metal is an intermediate layer in the multi-layer structure;

etching a plurality of layers of the multi-layer structure to expose the layer of conductive metal;

performing a first sputter etch of the layer of conductive metal using a methanol plasma;

performing a second sputter etch of the layer of conductive metal using a second plasma, wherein a portion of the layer of conductive metal that remains after the second sputter etch forms the one or more conductive lines;

forming a liner that surrounds the one or more conductive lines, subsequent to performing the second sputter etch; and

depositing a second dielectric layer on the multi-layer structure.