MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR

• US 20140129808A1
• Filed: 04/27/2012
• Published: 05/08/2014
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Naveh, Alon, Yosef, Yuval, Weissmann, Eliezer, Aggarwal, Anil, Rotem, Efraim, Mendelson, Avi, Ronen, Ronny, Ginzburg, Boris, Mishaeli, Michael, Koufaty, David A., Srinivasa, Ganapati, Therien, Guy, Hahn, Scott D.
• Granted Patent: US 10,185,566 B2
• Time in Patent Office: Days
• US Class Current: 712/225
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Claims

1. A multicore processor comprising:

a first core to independently execute instructions;

a second core to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core; and

a task controller coupled to the first and second cores to dynamically migrate a first process scheduled by the OS to the first core to the second core, where the dynamic migration is transparent to the OS.

2. The multicore processor of claim 1, wherein the task controller is to dynamically migrate the first process based at least in part on a performance state request received in a power controller from the OS.

3. The multicore processor of claim 2, wherein the task controller is to dynamically migrate the first process further based on performance monitor information obtained during execution of the first process on the first core.

4. The multicore processor of claim 1, wherein the first core is of a first instruction set architecture (ISA), and the second core is of a second ISA.

5. The multicore processor of claim 4, wherein the second core includes an emulation engine to emulate an instruction of the first ISA that is not included in the second ISA.

6. The multicore processor of claim 1, further comprising a plurality of first cores including the first core and a plurality of second cores including the second core, wherein a number of the plurality of first cores is asymmetric to a number of the plurality of second cores.

7. The multicore processor of claim 6, further comprising a first performance domain including at least one of the plurality of first cores, wherein the task controller is to dynamically migrate the first process from the first core to the second core based at least in part on a performance state request received in a power controller from the OS corresponding to the first performance domain.

8. The multicore processor of claim 7, wherein the task controller is to thereafter dynamically migrate the first process from the second core to the first core based on performance monitor information obtained during execution of the first process on the second core.

9. The multicore processor of claim 6, wherein the task controller is to dynamically migrate N processes each from one of the plurality of second cores to one of the plurality of first cores, when there are at least N unutilized cores of the plurality of first cores.

10. The multicore processor of claim 9, wherein the N processes are of a plurality of X processes executing on the plurality of second cores, X greater than N and wherein the N processes each have a higher utilization value than the remaining X−

N processes.

12. The processor of claim 1, further comprising an exception handling unit to handle an exception occurring during execution of the first process on the second core transparently to the OS.

11. (canceled)

13. (canceled)

14. (canceled)

15. (canceled)

16. A method comprising:

receiving a performance state update from an operating system (OS) in a controller of a multicore processor including a first plurality of cores and a second plurality of cores, the first plurality of cores visible to the OS and the second plurality of cores transparent to the OS and heterogeneous from the first plurality of cores, wherein the performance state update requests at least one of the first plurality of cores to operate at a requested performance state;

determining whether the requested performance state exceeds a guaranteed performance state and a threshold performance state; and

if so, migrating, transparently to the OS, at least one thread from at least one of the second plurality of cores to at least one of the first plurality of cores, wherein the OS allocated the at least one thread to one of the first plurality of cores.

17. The method of claim 16, further comprising determining whether the at least one thread has switched between the first plurality of cores and the second plurality of cores greater than a threshold number of times and maintaining the at least one thread on the first plurality of cores if the at least one thread has been switched between the first plurality of cores and the second plurality of cores greater than the threshold number of times.

18. The method of claim 16, further comprising identifying N unused ones of the first plurality of cores and identifying up to N threads executing on the second plurality of cores with highest performance monitor values over a threshold performance monitor value.

19. The method of claim 18, further comprising migrating the N threads from the second plurality of cores to the first plurality of cores.

20. (canceled)

21. (canceled)

22. A system comprising:

a multicore processor including a first plurality of cores and a second plurality of cores executing in a plurality of performance domains, the second plurality of cores heterogeneous to the first plurality of cores and transparent to an operating system (OS), and a power controller, wherein the power controller is to receive a performance state update from the OS for a first performance domain of the plurality of performance domains and performance monitor information from the first and second plurality of cores and to cause a context switch to dynamically migrate a process from execution on a second core of the second plurality of cores to a first core of the first plurality of cores transparently to the OS, based on the performance state update and the performance monitor information; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

23. The system of claim 22, wherein the second core includes an emulation logic to emulate an instruction of a first instruction set architecture (ISA), the second core of a different ISA than the first ISA.

24. The system of claim 22, wherein the power controller includes a counter to count a number of switches of the process between the first and second cores, wherein the task controller is to prevent the dynamic migration between the first core and the second core if the number of switches exceeds a threshold.

25. The system of claim 22, wherein a number of the first plurality of cores is different than a number of the second plurality of cores.

33. The system of claim 22, wherein the second plurality of cores is of a different instruction set architecture (ISA) than the first plurality of cores, and the different ISA is partially overlapping with an ISA of the first plurality of cores.

26. (canceled)

27. (canceled)

28. (canceled)

29. (canceled)

30. (canceled)

31. (canceled)

32. (canceled)