SOLID-STATE IMAGING APPARATUS AND METHOD FOR MANUFACTURING SAME

• US 20140131828A1
• Filed: 01/17/2014
• Published: 05/15/2014
• Est. Priority Date: 08/02/2011
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: ISONO, Shunsuke, UEDA, Tetsuya
• Granted Patent: US 9,184,316 B2
• Time in Patent Office: Days
• US Class Current: 257/459
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer
• CPC Class Codes: H01L 31/0224 Electrodes

Abstract

An insulating layer is layered above a substrate, and a plurality of pixel electrodes are formed above the insulating layer in a matrix with intervals therebetween. A photoelectric conversion layer and an opposing electrode are formed in respective order above the pixel electrodes. A dummy layer is formed above the insulating layer in a region that in plan-view is more peripheral than a pixel region in which the pixel electrodes are formed. The dummy layer is formed from the same material as the pixel electrodes. The dummy layer is composed of a plurality of dummy layer portions that are each equal to each of the pixel electrodes in terms of size in plan-view. The dummy layer functions as a support layer for planarization during polishing by chemical mechanical polishing.

Claims

1. A solid-state imaging apparatus comprising:

a substrate;

an insulating layer located above the substrate;

a plurality of first electrodes located above the insulating layer in a pixel region and arranged in a two dimensional array with intervals therebetween;

a second electrode covering the first electrodes in plan-view;

a photoelectric conversion layer located between the second electrode and the first electrodes;

a planarization support layer located above the insulating layer in a region that in plan-view is more peripheral than the pixel region; and

a connecting electrode configured to apply an electrical voltage to the second electrode and located in a region that in plan-view is more peripheral than the region in which the planarization support layer is located, wherein

the planarization support layer and the first electrodes are at a same layer level above the insulating layer.

2. The solid-state imaging apparatus of claim 1, wherein

the planarization support layer is composed of a plurality of planarization support layer portions that are arranged above the insulating layer with intervals therebetween.

3. The solid-state imaging apparatus of claim 2, wherein

the planarization support layer portions are arranged such as to surround an entire periphery of the pixel region.

4. The solid-state imaging apparatus of claim 2, wherein

each of the planarization support layer portions is equal to each of the first electrodes in terms of shape and size, and

the intervals between the planarization support layer portions are equal to the intervals between the first electrodes.

5. The solid-state imaging apparatus of claim 2, wherein

the planarization support layer portions are arranged such as to at least triply surround an entire periphery of the pixel region.

6. The solid-state imaging apparatus of claim 2, wherein

the insulating layer extends into an interval between each two of the first electrodes which are adjacent to one another, the insulating layer extending to a position that is higher than lower surfaces of the two first electrodes and lower than upper surfaces of the two first electrodes.

7. The solid-state imaging apparatus of claim 1, wherein

the planarization support layer and the first electrodes are made from similar metal materials.

8. The solid-state imaging apparatus of claim 1, wherein

the planarization support layer is made from a metal material including at least one selected from the group consisting of Cu, Al, Ti, Ta and W.

9. The solid-state imaging apparatus of claim 1, further comprising

a drive control circuit configured to perform input and output of signals with respect to the first electrodes and the second electrode, the drive control circuit being located in at least one of the substrate and the insulating layer, in a region that in plan-view is more peripheral than the pixel region, wherein

the planarization support layer is light-blocking and covers the drive control circuit in plan-view.

10. The solid-state imaging apparatus of claim 9, wherein

the planarization support layer is at least partially composed of a plurality of planarization support layer portions arranged above the insulating layer with intervals therebetween, in a region corresponding to the drive control circuit,

each of the first electrodes and each of the plurality of planarization support layer portions has an oblong shape in plan-view, and

at least one side of each of the planarization support layer portions is at least three times as long as a correspondingly orientated side of each of the first electrodes.

11. The solid-state imaging apparatus of claim 1, wherein

the planarization support layer is not electrically connected to the first electrodes, the second electrode or the photoelectric conversion layer.

12. The solid-state imaging apparatus of claim 1, further comprising

a plug located below the planarization support layer and passing through the insulating layer, wherein

the planarization support layer is connected to the plug.

13. The solid-state imaging apparatus of claim 1, wherein

each of the first electrodes includes at least one selected from the group consisting of TiN, Ti, Al, Ta, TaN, Cu and W.

14. The solid-state imaging apparatus of claim 1, further comprising

a plurality of readout circuits configured to readout an electrical charge signal generated in the photoelectric conversion layer, the readout circuits being located in at least one of the substrate and the insulating layer in one-to-one correspondence with the first electrodes, wherein

each of the first electrodes is electrically connected to a corresponding one of the readout circuits.

15. A method for manufacturing a solid-state imaging apparatus, the method comprising:

a step (a) of preparing a substrate;

a step (b) of layering an insulating layer above the substrate;

a step (c) of forming a plurality of metal films, for first electrode use, above the insulating layer in a pixel region, the metal films being formed in a two dimensional array with intervals therebetween;

a step (d) of forming a planarization support layer above the insulating layer in a region that in plan-view is more peripheral than the pixel region;

a step (e) of forming an insulating material layer over upper surfaces of the metal films and the planarization support layer, and also over the insulating layer in the intervals between the metal films;

a step (f) of polishing the insulating layer, the insulating material layer, the metal films and the planarization support layer by performing chemical mechanical polishing;

a step (g) of forming a photoelectric conversion layer such as to entirely cover a plurality of first electrodes which are formed by the polishing of the metal films;

a step (h) of forming a second electrode above the photoelectric conversion layer; and

a step (i) of forming a connecting electrode, configured to apply an electrical voltage to the second electrode, above the insulating layer in a region that in plan-view is more peripheral than the planarization support layer, wherein

the planarization support layer and the first electrodes are at a same layer level above the insulating layer.