INTEGRATED CIRUIT INCLUDING AN FIN-BASED DIODE AND METHODS OF ITS FABRICATION

• US 20140131831A1
• Filed: 11/12/2012
• Published: 05/15/2014
• Est. Priority Date: 11/12/2012
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wei, Andy C., Korablev, Konstantin, Tambwe, Francis
• Application Number:
  US13/674,311
• Publication Number:
  US 20140131831A1
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin.

Claims

1. A method of forming a diode, comprising:

forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer, the at least one fin extending from a bottom end adjacent the substrate layer to a top end;

adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin; and

etching away a portion of the STI oxide layer to expose the top end of the at least one fin.

2. A method as set forth in claim 1 further comprising forming an n-well in the substrate layer below the bottom end of the at least one fin.

3. A method as set forth in claim 2 wherein said forming an n-well is performed prior to said adding a cathode implant and said adding an anode implant.

4. A method as set forth in claim 1 wherein said etching away a portion of the STI oxide layer occurs after adding the cathode implant and the anode implant.

5. A method as set forth in claim 1 further comprising forming a well tap below the at least one fin.

6. A method as set forth in claim 5 wherein said forming a well tap is further defined as implanting a p-well in the substrate in the first region below the bottom end of the at least one fin.

7. A method as set forth in claim 6 wherein said implanting a p-well and said adding a cathode implant are performed concurrently.

8. A method as set forth in claim 1 further comprising epitaxially growing a semiconductor material on the exposed top end of the at least one fin.

9. A method as set forth in claim 1 further comprising disposing a dummy gate above the top end of the at least one fin.

10. A method as set forth in claim 1 further comprising disposing a self-aligning contact above the top end of the at least one fin.

11. A method of fabricating an integrated circuit, comprising:

establishing at least one FinFET on a substrate layer;

establishing at least one diode including

forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above the substrate layer, the at least one fin extending from a bottom end adjacent the substrate layer to a top end;

adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin; and

etching away a portion of the STI oxide layer to expose the top end of the at least one fin.

12. A method as set forth in claim 11 further comprising forming an n-well in the substrate layer below the bottom end of the at least one fin.

13. A method as set forth in claim 12 wherein said forming an n-well is performed prior to said adding a cathode implant and said adding an anode implant.

14. A method as set forth in claim 11 wherein said etching away a portion of the STI oxide layer occurs after adding the cathode implant and the anode implant.

15. A method as set forth in claim 11 further comprising forming a well tap below the at least one fin.

16. A method as set forth in claim 15 wherein said forming a well tap is further defined as implanting a p-well in the substrate in the first region below the bottom end of the at least one fin.

17. A method as set forth in claim 16 wherein said implanting a p-well and said adding a cathode implant are performed concurrently.

18. An integrated circuit including a semiconductor diode, said diode comprising:

a substrate layer;

a shallow trench isolation (STI) oxide layer disposed above said substrate layer;

at least one fin disposed at least partially in the STI oxide layer, the at least one fin extending from a bottom end to a top end;

a cathode implant formed in a first region of said at least one fin and extending into said substrate below said at least one fin; and

an anode implant formed in a second region of said at least one fin and extending into said substrate below said at least one fin such that a junction is formed in said substrate below said at least one fin.

19. An integrated circuit as set forth in claim 18 further comprising a well tap formed in the substrate layer below said at least one fin.