GAN VERTICAL BIPOLAR TRANSISTOR

• US 20140131837A1
• Filed: 11/13/2012
• Published: 05/15/2014
• Est. Priority Date: 11/13/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Avogy Inc.
• Inventors: Nie, Hui, Edwards, Andrew, Kizilyalli, Isik, Bour, Dave
• Granted Patent: US 8,823,140 B2
• Time in Patent Office: Days
• US Class Current: 257/565
• CPC Class Codes: H01L 21/04 the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42304 Base electrodes for bipolar transistors
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors

Abstract

An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.

Claims

1. A method for fabricating a vertical bipolar transistor, the method comprising:

providing a III-nitride base structure of a first conductivity type;

forming a III-nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein;

the first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure;

a first dielectric layer is coupled to the second surface of the III-nitride emitter structure; and

the III-nitride emitter structure has a sidewall adjacent to an exposed portion of the surface of the III-nitride base structure;

forming a spacer coupled to the sidewall of the III-nitride emitter structure and the exposed portion of the surface of the III-nitride base structure; and

forming a base contact structure comprising a III-nitride material coupled to the spacer, the exposed portion of the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.

2. The method of claim 1 further comprising:

forming a second dielectric layer coupled to the base contact structure and the first dielectric layer;

removing at least a portion of the second dielectric layer and the first dielectric layer to expose a portion of the second surface of the III-nitride emitter structure; and

forming a metal structure coupled to the exposed portion of the second surface of the III-nitride emitter structure.

3. The method of claim 2 wherein:

removing at least a portion of the second dielectric layer and the first dielectric layer is performed by etching; and

an etch mask used in the removing the at least a portion of the second dielectric layer is also used in the removing the at least a portion of the first dielectric layer.

4. The method of claim 1 further comprising forming the III-nitride material of the base contact structure using epitaxial regrowth.

5. The method of claim 1 further comprising forming one or more edge termination structures.

6. The method of claim 5 wherein forming the one or more edge termination structures comprises implanting ions into one or more III-nitride structures.

7. The method of claim 1 wherein the III-nitride base structure comprises indium gallium nitride (InGaN).

8. The method of claim 1 wherein the III-nitride emitter structure comprises at least two III-nitride epitaxial layers, and forming the III-nitride emitter structure comprises:

forming a first III-nitride epitaxial layer coupled to the surface of the III-nitride base structure, the first III-nitride epitaxial layer having a first dopant concentration; and

forming a second III-nitride epitaxial layer coupled to the first III-nitride epitaxial layer, the second III-nitride epitaxial layer having a second dopant concentration;

wherein the first dopant concentration is less than the second dopant concentration.

9. The method of claim 1 wherein forming the base contact structure comprises forming a metal layer coupled to the III-nitride material of the base contact structure.

10. A semiconductor device comprising:

a III-nitride base structure of a first conductivity type;

a III-nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein the first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure;

a first dielectric layer coupled to the second surface of the III-nitride emitter structure;

a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure; and

a base contact structure comprising a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.

11. The semiconductor device of claim 10 further comprising:

a second dielectric layer coupled to the base contact structure and the first dielectric layer; and

a metal structure coupled to of the second surface of the III-nitride emitter structure.

12. The semiconductor device of claim 10 further comprising one or more edge termination structures.

13. The semiconductor device of claim 10 wherein the one or more edge termination structures comprises at least one portion of one or more III-nitride structures adjacent to the base contact structure, the at least one portion implanted with ions.

14. The semiconductor device of claim 10 wherein the III-nitride emitter structure comprises:

a first III-nitride epitaxial layer coupled to the surface of the III-nitride base structure, the first III-nitride epitaxial layer having a first dopant concentration; and

a second III-nitride epitaxial layer coupled to the first III-nitride epitaxial layer, the second III-nitride epitaxial layer having a second dopant concentration;

wherein the first dopant concentration is less than the second dopant concentration.

15. The semiconductor device of claim 10 wherein the base contact structure comprises a metal layer coupled to the III-nitride material of the base contact structure.

16. A method for fabricating a vertical bipolar transistor, the method comprising:

providing a first III-nitride layer of a first conductivity type;

forming at least one III-nitride layer of a second conductivity type coupled to the first III-nitride layer;

forming a first dielectric layer coupled to the at least one III-nitride layer;

removing at least a portion of the first dielectric layer and the at least one III-nitride layer to;

expose a surface of the first III-nitride layer, and

form a layered structure comprising at least a portion of the at least one III-nitride layer and the first dielectric layer;

forming a spacer coupled to a sidewall of the layered structure; and

forming a second III-nitride layer of the first conductivity type coupled to the spacer, the exposed surface of the first III-nitride layer, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the second III-nitride layer and the at least one III-nitride layer.

17. The method of claim 16 wherein further comprising:

removing at least a portion of the second III-nitride layer to expose a surface of the first dielectric layer;

forming a second dielectric layer coupled to the second III-nitride layer and the first dielectric layer;

removing at least a portion of the second dielectric layer and the first dielectric layer to expose a surface of the at least one III-nitride layer; and

forming a metal structure coupled to the exposed surface of the at least one III-nitride layer.

18. The method of claim 16 further comprising forming second III-nitride layer using epitaxial regrowth.

19. The method of claim 16 further comprising forming one or more edge termination structures.

20. The method of claim 16 wherein forming the at least one III-nitride layer comprises:

forming a third III-nitride epitaxial layer coupled to the first III-nitride layer, the third III-nitride epitaxial layer having a first dopant concentration; and

forming a fourth III-nitride epitaxial layer coupled to the third III-nitride epitaxial layer, the fourth III-nitride epitaxial layer having a second dopant concentration;

wherein the first dopant concentration is less than the second dopant concentration.

21. The method of claim 16 further comprising forming a metal layer coupled to the second III-nitride layer.