POWER FACTOR CORRECTION APPARATUS, POWER SUPPLYING APPARATUS AND MOTOR DRIVING APPARATUS HAVING THE SAME

• US 20140132191A1
• Filed: 02/01/2013
• Published: 05/15/2014
• Est. Priority Date: 11/15/2012
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: HEO, Chang Jae
• Granted Patent: US 9,148,062 B2
• Time in Patent Office: Days
• US Class Current: 318/400.27
• CPC Class Codes: G05F 1/613 using semiconductor devices in parallel with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: H02M 1/0054 Transistor switching losses periodically suspending operation of switching converter in low power mode H02M1/0035
• CPC Class Codes: H02M 1/42 Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/33546 with automatic control of the output voltage or current H02M3/33561 takes precedence
• CPC Class Codes: H02M 5/458 using semiconductor devices only
• CPC Class Codes: H02P 23/26 Power factor control [PFC]
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

There are provided a power factor correction apparatus capable of driving a main switch and an auxiliary switch using a single driving signal, and a power supplying apparatus and a motor driving apparatus having the same, the power factor correction apparatus including: a power factor correction unit having a main switch switching input power to correct a power factor of the input power and an auxiliary switch turned on before the main switch is turned on to form a transfer path for surplus power; and a control unit controlling operations of the main switch and the auxiliary switch based on a single input signal.

Claims

1. A power factor correction apparatus comprising:

a power factor correction unit having a main switch switching input power to correct a power factor of the input power and an auxiliary switch turned on before the main switch is turned on to form a transfer path for surplus power; and

a control unit controlling operations of the main switch and the auxiliary switch based on a single input signal.

2. The power factor correction apparatus of claim 1, wherein the control unit includes:

a main signal generator generating a main signal by delaying a rising timing and a falling timing of the single input signal by a preset time, respectively; and

an auxiliary signal generator generating an auxiliary signal having the same rising timing as that of the single input signal and a falling timing shortened as compared to that of the single input signal.

3. The power factor correction apparatus of claim 2, wherein the control unit further includes an output unit receiving the main signal of the main signal generator and the auxiliary signal of the auxiliary signal generator to output a main switching signal and an auxiliary switching signal, respectively.

4. The power factor correction apparatus of claim 3, wherein the output unit includes:

a first output unit having a first inverter inverting a signal level of the main signal of the main signal generator and a first transistor unit having a first p-channel metal oxide semiconductor (PMOS) transistor connected between a driving power supply and a ground and a first n-channel metal oxide semiconductor (NMOS) transistor connected between the first PMOS transistor and the ground and outputting the main switching signal obtained by adjusting a rising timing and a falling timing of the main signal; and

a second output unit having a second inverter inverting a signal level of the auxiliary signal of the auxiliary signal generator and a second transistor unit having a second PMOS transistor connected between the driving power supply and the ground and a second NMOS transistor connected between the second PMOS transistor and the ground and outputting the auxiliary switching signal obtained by adjusting the rising timing and the falling timing of the auxiliary signal the auxiliary switching signal having a rising timing delayed as compared to that of the input signal.

5. The power factor correction apparatus of claim 4, wherein the first transistor unit includes at least one resistor connected between the first PMOS transistor and the first NMOS transistor or connected between a connection point of the first PMOS transistor and the first NMOS transistor and an output terminal.

6. The power factor correction apparatus of claim 4, wherein the second transistor unit includes at least one resistor connected between the second PMOS transistor and the second NMOS transistor or connected between a connection point of the second PMOS transistor and the second NMOS transistor and an output terminal.

7. The power factor correction apparatus of claim 2, wherein each of the main signal generator and the auxiliary signal generator includes a delay unit delaying the rising timing or the falling timing of the single input signal.

8. The power factor correction apparatus of claim 7, wherein the auxiliary signal generator further includes an inverter inverting a level of an output signal of the delay unit, and an AND gate performing a logical AND operation between an output signal of the inverter and the single input signal.

9. The power factor correction apparatus of claim 7, wherein the auxiliary signal generator delays a rising timing or a falling timing of the signal delayed by the main signal generator.

10. The power factor correction apparatus of claim 7, wherein the delay unit includes at least two inverters connected to each other in series and a capacitor connected between a connection point of the two inverters and the ground.

11. The power factor correction apparatus of claim 10, wherein the capacitor of the delay unit of the main signal generator has capacitance higher than that of the capacitor of the delay unit of the auxiliary signal generator.

12. The power factor correction apparatus of claim 10, wherein the delay unit further includes at least two of a transistor, a resistor, and a current source that are connected between the two inverters.

13. The power factor correction apparatus of claim 1, wherein the power factor correction unit further includes:

a first inductor having one end receiving rectified power and the other end connected to a drain of the main switch; and

a second inductor having one end connected to the other end of the first inductor and the other end connected to a drain of the auxiliary switch.

14. A power supplying apparatus comprising:

a power factor correction circuit including a power factor correction unit having a main switch switching rectified power to correct a power factor of input power, an auxiliary switch turned on before the main switch is turned on to form a transfer path for surplus power, a first inductor having one end receiving the rectified power and the other end connected to a drain of the main switch, and a second inductor having one end connected to the other end of the first inductor and the other end connected to a drain of the auxiliary switch, and including a control unit controlling operations of the main switch and the auxiliary switch based on a single input signal; and

a power conversion circuit converting the power having the corrected power factor from the power factor correction circuit into power having a preset voltage level.

15. The power supplying apparatus of claim 14, wherein the power conversion circuit is an inverter circuit inverting the power having the corrected power factor to convert the power into preset alternating current (AC) power.

16. The power supplying apparatus of claim 14, wherein the control unit includes:

a main signal generator including a delay unit delaying a rising timing and a falling timing of the single input signal by a preset time, respectively, to generate a main signal; and

an auxiliary signal generator including another delay unit to generate an auxiliary signal having the same rising timing as that of the single input signal and a falling timing shortened as compared to that of the single input signal.

17. The power supplying apparatus of claim 16, wherein the control unit further includes an output unit receiving the main signal of the main signal generator and the auxiliary signal of the auxiliary signal generator to output a main switching signal and an auxiliary switching signal, respectively.

18. The power supplying apparatus of claim 17, wherein the output unit includes:

a first output unit including a first inverter inverting a signal level of the main signal of the main signal generator and a first transistor unit having a first p-channel metal oxide semiconductor (PMOS) transistor connected between a driving power supply and a ground and a first n-channel metal oxide semiconductor (NMOS) transistor connected between the first PMOS transistor and the ground and outputting the main switching signal obtained by adjusting a rising timing and a falling timing of the main signal; and

a second output unit including a second inverter inverting a signal level of the auxiliary signal of the auxiliary signal generator and a second transistor unit having a second PMOS transistor connected between the driving power supply and the ground and a second NMOS transistor connected between the second PMOS transistor and the ground and outputting the auxiliary switching signal obtained by adjusting the rising timing and the falling timing of the auxiliary signal, the auxiliary switching signal having a rising timing delayed as compared to that of the input signal.

19. The power supplying apparatus of claim 18, wherein the first transistor unit includes at least one resistor connected between the first PMOS transistor and the first NMOS transistor or connected between a connection point of the first PMOS transistor and the first NMOS transistor and an output terminal, and

the second transistor unit includes at least one resistor connected between the second PMOS transistor and the second NMOS transistor or connected between a connection point of the second PMOS transistor and the second NMOS transistor and an output terminal.

20. The power supplying apparatus of claim 16, wherein the auxiliary signal generator further includes an inverter inverting a level of an output signal of the delay unit, and an AND gate performing a logical AND operation between an output signal of the inverter and the single input signal.

21. The power supplying apparatus of claim 16, wherein the auxiliary signal generator delays a rising timing or a falling timing of the signal delayed by the main signal generator.

22. The power supplying apparatus of claim 16, wherein the delay unit includes at least two inverters connected to each other in series and a capacitor connected between a connection point of the two inverters and the ground, and

the capacitor of the delay unit of the main signal generator has capacitance higher than that of the capacitor of the delay unit of the auxiliary signal generator.

23. The power supplying apparatus of claim 16, wherein the delay unit further includes at least two of a transistor, a resistor, and a current source that are connected between the two inverters.

24. A motor driving apparatus comprising:

a power factor correction circuit including a power factor correction unit having a main switch switching rectified power to correct a power factor of input power, an auxiliary switch turned on before the main switch is turned on to form a transfer path for surplus power, a first inductor having one end receiving the rectified power and the other end connected to a drain of the main switch, and a second inductor having one end connected to the other end of the first inductor and the other end connected to a drain of the auxiliary switch, and including a control unit controlling operations of the main switch and the auxiliary switch based on a single input signal; and

an inverter circuit inverting the power having the corrected power factor from the power factor correction circuit into preset AC power to drive a motor.

25. The motor driving apparatus of claim 24, wherein the control unit includes:

a main signal generator generating a main signal by delaying a rising timing and a falling timing of the single input signal by a preset time, respectively; and

an auxiliary signal generator generating an auxiliary signal having the same rising timing as that of the single input signal and a falling timing shortened as compared to that of the single input signal.

26. The motor driving apparatus of claim 25, wherein the control unit further includes an output unit receiving the main signal of the main signal generator and the auxiliary signal of the auxiliary signal generator to output a main switching signal and an auxiliary switching signal, respectively.

27. The motor driving apparatus of claim 26, wherein the output unit includes:

a first output unit including a first inverter inverting a signal level of the main signal of the main signal generator and a first transistor unit having a first p-channel metal oxide semiconductor (PMOS) transistor connected between a driving power supply and a ground and a first n-channel metal oxide semiconductor (NMOS) transistor connected between the first PMOS transistor and the ground and outputting the main switching signal obtained by adjusting a rising timing and a falling timing of the main signal; and

a second output unit including a second inverter inverting a signal level of the auxiliary signal of the auxiliary signal generator and a second transistor unit having a second PMOS transistor connected between the driving power supply and the ground and a second NMOS transistor connected between the second PMOS transistor and the ground and outputting the auxiliary switching signal obtained by adjusting the rising timing and the falling timing of the auxiliary signal, the auxiliary switching signal having a rising timing delayed as compared to that of the input signal.

28. The motor driving apparatus of claim 27, wherein the first transistor unit includes at least one resistor connected between the first PMOS transistor and the first NMOS transistor or connected between a connection point of the first PMOS transistor and the first NMOS transistor and an output terminal, and

the second transistor unit includes at least one resistor connected between the second PMOS transistor and the second NMOS transistor or connected between a connection point of the second PMOS transistor and the second NMOS transistor and an output terminal.

29. The motor driving apparatus of claim 25, wherein the auxiliary signal generator further includes an inverter inverting a level of an output signal of the delay unit, and an AND gate performing a logical AND operation between an output signal of the inverter and the single input signal.

30. The motor driving apparatus of claim 25, wherein the auxiliary signal generator delays a rising timing or a falling timing of the signal delayed by the main signal generator.

31. The motor driving apparatus of claim 25, wherein the delay unit includes at least two inverters connected to each other in series and a capacitor connected between a connection point of the two inverters and the ground, and

the capacitor of the delay unit of the main signal generator has capacitance higher than that of the capacitor of the delay unit of the auxiliary signal generator.

32. The motor driving apparatus of claim 25, wherein the delay unit further includes at least two of a transistor, a resistor, and a current source that are connected between the two inverters.