SYSTEM AND METHOD FOR MRAM HAVING CONTROLLED AVERAGABLE AND ISOLATABLE VOLTAGE REFERENCE
First Claim
1. A Non-Volatile Resistive memory comprising:
- a plurality of reference cells associated with at least one array of bitcells (I/O), wherein at least two of the plurality of reference cells are coupled to a common node; and
a plurality of sense amplifiers associated with the I/Os, wherein at least one sense amplifier is coupled to the common node.
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Accused Products
Abstract
A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.
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Citations
19 Claims
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1. A Non-Volatile Resistive memory comprising:
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a plurality of reference cells associated with at least one array of bitcells (I/O), wherein at least two of the plurality of reference cells are coupled to a common node; and a plurality of sense amplifiers associated with the I/Os, wherein at least one sense amplifier is coupled to the common node. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for a Non-Volatile Resistive memory comprising:
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providing at least one array of bitcells (I/O), each I/O having at least one reference cell having a reference voltage output node and a corresponding I/O reference line; selecting at least two of the I/O reference lines for a common reference line; and coupling at least two of the selected I/O reference lines to form a common reference line. - View Dependent Claims (8, 9, 10, 11)
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12. A Non-Volatile Resistive bitcell array memory comprising:
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means for generating a first reference voltage; means for generating a second reference voltage; means for providing a first sensing reference and a second sensing reference, including means for selectively combining the first reference voltage and the second reference voltage into a common voltage and for selectively providing the common voltage as the first sensing reference, and means for selectively providing the first reference voltage as the first sensing reference; means for sensing a voltage of a first array of bitcells relative to the first sensing reference; and means for sensing a voltage of a second array of bitcells relative to the second sensing reference. - View Dependent Claims (13, 14)
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15. A method for a Non-Volatile Resistive memory comprising steps of:
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providing at least one array of bitcells (I/O), each I/O having at least one reference cell having a reference voltage output node and a corresponding I/O reference line; selecting at least two of the I/O reference lines for a common reference line; and coupling at least two of the selected I/O reference lines to form a common reference line. - View Dependent Claims (16, 17, 18, 19)
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Specification