SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM

• US 20140133255A1
• Filed: 01/22/2014
• Published: 05/15/2014
• Est. Priority Date: 03/12/2010
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Kazuhiko Kajigaya
• Inventors: KAJIGAYA, Kazuhiko
• Granted Patent: US 8,867,294 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type

Abstract

A semiconductor device comprises a first memory cell array, a register storing information of whether or not one of the word lines in an active state exists in a unit area and storing address information, and a control circuit controlling a refresh operation for a refresh word line based on the information in the register when receiving a refresh request. When the one of the word lines in an active state does not exist, memory cells connected to the refresh word line are refreshed. When the one of the word lines in an active state exists, the one of the word lines in an active state is set into an inactive state temporarily and the memory cells connected to the refresh word line are refreshed after precharging bit lines of the memory cells.

Claims

1. A semiconductor device comprising:

a unit area including a first memory cell array that includes a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines;

a register storing state information of whether or not at least one of the word lines is in an active state and address information of the at least one of the word lines; and

a control circuit controlling a refresh operation on a refresh word line in the first memory cell array based on the state and address information stored in the register when the control circuit receives a refresh command, the refresh word line being selected in response to the refresh command,

wherein when the state information of the register indicates that the at least one of the word lines is in the active state, in the refresh operation the control circuit sets the at least one of the word lines in the active state into an inactive state temporarily, and while the at least one of the word lines is in the inactive state, the control circuit refreshes the memory cells connected to the refresh word line.

2. The semiconductor device according to claim 1, wherein the unit area is the first memory cell array.

3. The semiconductor device according to claim 1,

wherein the unit area is an area including the first memory cell array and one or two memory cell arrays each sharing a sense amplifier row with the first memory cell array, the one or two memory cell arrays each being the first memory cell array.

4. The semiconductor device according to claim 1, wherein the unit area is a first block including N memory cell arrays aligned in a predetermined direction, each of the N memory cell arrays being the first memory cell array.

5. The semiconductor device according to claim 4, wherein M blocks each being the first block forms a first bank, and the one of the word lines in the active state exists in the first bank.

6. The semiconductor device according to claim 5, wherein L banks each being the first bank are provided, and the one of the word lines in the active state exists independently in each of the L banks.

7. The semiconductor device according to claim 6, wherein the refresh operation is simultaneously performed for the M blocks in selected one of the banks.

8. The semiconductor device according to claim 6, wherein the refresh operation is simultaneously performed for L×

K blocks obtained by selecting K blocks from each of the L banks.

9. The semiconductor device according to claim 1, wherein the control circuit comprises a first selector selectively outputting the address information stored in the register, an externally input address, and a refresh address outputted from a refresh address counter.

10. The semiconductor device according to claim 1, wherein the control circuit comprises a second selector selectively operating a first control circuit controlling a refresh operation performed when the one of the word lines in the active state exists, a second control circuit controlling a refresh operation performed when the one of the word lines in the active state does not exist, and a third control circuit controlling a normal operation of the first memory cell array.

11. The semiconductor device according to claim 1 further comprising a relief circuit replacing a defective word line included in the plurality of word line with a redundancy word line,

wherein the control circuit controls the relief circuit to replace the refresh word line with the redundancy word line as a relief destination when the refresh word line is the defective word line, and performs a refresh operation of memory cells connected to the redundant word line.

12. A refresh control method of a semiconductor device having a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines, the method comprising:

determining whether or not at least one of the word lines in an active state exists in a unit area including the memory cell array when receiving a refresh request of a refresh word line selected in the memory cell array;

refreshing the memory cells connected to the refresh word line if a determination result indicates that the one of the word lines in the active state does not exist; and

refreshing the memory cells connected to the refresh word line after temporarily changing the one of the word lines in the active state into an inactive state so as to precharge the plurality of bit lines if the determination result indicates that the one of the word lines in the active state exists.

13. The refresh control according to claim 12,

wherein the semiconductor device further comprises a relief circuit replacing a defective word line included in the plurality of word line with a redundancy word line,

and when the refresh word line is the defective word line, the refresh word line is replaced with the redundancy word line as a relief destination and memory cells connected to the redundant word line are refreshed.

14. A semiconductor device comprising:

a memory cell array including a first memory cell block that has a plurality of first word lines, first bit lines, and first memory cells provided at intersections of the first word lines and the first bit lines, respectively;

a register storing either one of first information that at least one of the first word lines is activated and second information that any one of the first word lines is not activated; and

a control circuit performing a refresh operation on one of the first word lines, when the register stores the first information, such that the control circuit inactivate the at least one of the first word lines that is activated, activating the one of the first word lines to perform the refresh operation on the one of the first word lines, inactivating the one of the first word lines after the refresh operation, and then activating the at least one of the first word lines.

15. The semiconductor device as claimed in claim 15, further comprising a command decoder coupled to a plurality of external command terminals, the command decoder generating an internal refresh command when a set of the external command terminals is supplied with an external refresh command, and the control circuit performing the refresh operation in response to the internal refresh command.

16. The semiconductor device as claimed in claim 15, wherein the control circuit performs an additional refresh operation on the one of the first word lines, when the register stores the second information, such that the control circuit activates the one of the first word lines to perform the refresh operation on the one of the first word lines and inactivates the one of the word lines after the refresh operation without inactivating any of the first word lines except for the one of the first word lines.