ARCHITECTURES FOR DATA ANALYTICS USING COMPUTATIONAL NAND MEMORY

• US 20140136761A1
• Filed: 03/14/2013
• Published: 05/15/2014
• Est. Priority Date: 11/09/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Li, Yan, Busch, John R., Sprouse, Steven T.
• Granted Patent: US 8,792,279 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 9/5072 Grid computing
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Abstract

A data analytic system allows for analytic operations be moved from a server on to a solid state drive (SSD) type analytic system, where a CAM NAND structure can be used in the analytic operations. The server can run a software using database language can issue command to the analytic system. On the data analytic system (that can interface with common, existing database language), the software commands are translated into firmware language and broken down into multiple small tasks. The small tasks are executed on the SSD flash controllers or on NAND flash according to the task specifications. The mid-product from the NAND flash or the SSD controllers can be merged within each SSD blade and also further merged on the top server level.

Claims

1. A method of performing data analytics using a server and a memory system connected thereto, where the memory system comprises control circuitry and a plurality of sets of memory arrays having a NAND type of architecture, the control circuitry including a plurality of memory controllers each associated with a corresponding set of memory arrays, the method comprising:

running software on the server that issues commands to the memory system to perform one or more data analytic operations;

receiving the issued commands on the memory system;

translating of the received commands into a plurality of analytic tasks by firmware operating on the control circuitry;

distributing by the firmware of the analytic tasks across the memory controllers to be executed by the memory controllers and corresponding sets memory of memory arrays;

executing the analytic tasks on the memory controllers and corresponding sets memory of memory arrays, wherein each of the analytic tasks are executed on the memory controller, the associated sets of memory arrays, or a combination thereof as specified by the firmware;

merging results from the analytic tasks by the firmware; and

transferring out the merged results to the server.

2. The method of claim 1, further comprising:

receiving the merged results at the server; and

subsequently further merging the received results by the software to complete the analytic operations.

3. The method of claim 1, wherein the software is proprietary.

4. The method of claim 1, wherein the software is open source.

5. The method of claim 1, wherein the server and the memory system interface using a database language.

6. The method of claim 1, wherein the analytic operations are performed on data stored on the memory system.

7. The method of claim 1, wherein the analytic operations are performed on data received from the server.

8. The method of claim 1, wherein performing analytic tasks on the memory arrays includes writing data sets oriented along bit lines of the memory arrays.

9. The method of claim 8, further comprising:

transposing on the memory system of the data sets from a word line orientation to a bit line orientation prior to writing the data sets oriented along bit lines of the memory arrays.

10. The method of claim 1, wherein the analytic operations include a plurality of jobs, wherein analytic tasks corresponding to differing jobs are executed in parallel on different memory controllers and associated sets of memory arrays.

35. The method of claim 1, wherein the memory arrays are of a 3D-type architecture.

11. A method of performing analytic operations on a plurality of sets of data, comprising:

receiving on a memory system from a server a plurality of data sets and instructions for analytics to perform upon the data sets, wherein the memory system includes control circuitry having one or more memory controllers and one or more memory circuits each having one or more memory arrays of non-volatile memory cells having a NAND type of architecture;

breaking down by the control circuitry of the received instructions into a plurality of sub-operations and assigning one or more of the sub-operations to be performed on the control circuitry and one or more of the sub-operations to be performed within the memory circuits;

deriving from the received data sets by the control circuitry of a plurality of corresponding first derived data sets for use in the sub-operations to be performed within the memory circuits;

writing the first derived datasets into one or more of the memory arrays, wherein the first derived data sets are written into the memory arrays oriented along bit lines;

subsequently performing the sub-operations; and

providing the result of the analytics performed on the data sets to the server.

12. The method of claim 11, wherein the first derived data sets are the same as the corresponding received data sets.

13. The method of claim 11, wherein the received data sets each include a plurality of data items and the first derived data sets are a subset of the data items the corresponding received data sets.

14. The method of claim 11, wherein the writing the first derived data sets into one or more of the memory arrays includes writing individual ones of the first derived data sets into the memory arrays multiple times in differing locations.

15. The method of claim 11, further comprising:

deriving from the received data sets by the control circuitry of a plurality of corresponding second derived data sets;

writing the second derived data sets into one or more of the memory arrays, wherein the first derived data sets are written into the memory arrays oriented along word lines;

maintaining by the control circuitry of a correspondence between the locations of the first and second derived data sets that correspond to the same received data set,

wherein sub-operations performed with the memory circuits use the first and second derived data sets.

16. The method of claim 15, wherein said correspondences is maintained through a mapping formula.

17. The method of claim 15, wherein said correspondences is maintained through a mapping table in memory system.

18. The method of claim 15, wherein the received data sets each include a plurality of data items, the first derived data sets are a first subset of the data items the corresponding received data sets, and the second derived data sets are a second subset of the data items the corresponding received data sets.

19. The method of claim 11, wherein the received instruction are for sub-operations of one or more analytic operations for which one or more additional sub-operations are performed by the server.

20. The method of claim 11, wherein the control circuitry further includes a memory system controller and the received instruction are for sub-operations of one or more analytic operations for which one or more additional sub-operations are performed by the memory system controller.

21. The method of claim 11, wherein the operations assigned to be performed within the memory circuits include one or more of:

a search function;

a match function;

determination of a maximum;

determination of a minimum;

a greater than operation;

a less than operation;

an addition operation; and

a subtraction operation.

22. The method of claim 11, wherein the operations assigned to be performed on the control circuitry include one or more of:

a sort operation;

a merge operation;

an addition operation;

a subtraction operation;

a division operation; and

an exponential operation.

23. The method of claim 11, wherein the control circuitry includes multiple memory controllers each controlling an associated set of one or more associated memory circuits, and wherein a plurality of the sub-operations are distributed across a plurality of the memory controller and the corresponding associated memory arrays.

24. The method of claim 23, wherein the plurality of the memory controllers issue parallel command sequences to the corresponding associated memory arrays to execute the distributed sub-operations in parallel.

25. The method of claim 24, wherein the parallel command sequences correspond to different analytic jobs.

26. The method of claim 11, further comprising:

transposing the first derived data sets from a word line orientation to a bit line orientation prior to said writing the first derived data sets into one or more of the memory arrays.

27. The method of claim 26, wherein the determination of the content of the first derived data sets and the transposing thereof is dependent on the received instructions.

28. The method of claim 11, wherein the memory system performs the analytics based upon firmware on the control circuitry.

29. The method of claim 11, wherein the control circuitry is optimized to perform a selected set of analytic operations.

30. The method of claim 11, wherein one or more of the sub-operations to be performed with the memory circuits are performed in parallel with one or more of the sub-operations to be performed on the control circuitry.

31. The method of claim 30, wherein the control circuitry performs a counting operation concurrently with one or more sensing operations being performed on the memory circuits.

32. The method of claim 11, wherein the control circuitry includes a plurality of memory controllers and an interface controller, wherein the interface controller coordinates the merging of results of sub-operations received from the memory controllers.

33. The method of claim 11, wherein the control circuitry includes a plurality of memory controllers and an interface controller, wherein the interface controller transfers out to the server results of sub-operations received from the memory controllers for merging on the server.

34. The method of claim 11, wherein while executing the analytics, the control circuitry suspends data maintenance operations for the memory system.

36. The method of claim 11, wherein the memory arrays are of a 3D-type architecture.