SOLID-STATE STORAGE MANAGEMENT

• US 20140136769A1
• Filed: 01/20/2014
• Published: 05/15/2014
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Franceschini, Michele M., Jagmohan, Ashish
• Granted Patent: US 9,858,015 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Solid-state storage management for a system, the management including establishing, externally to a solid-state storage board, a correspondence between a first logical address and a first physical address on solid-state storage devices located on the solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses. The correspondence between the first logical address and the first physical address is accepted by the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in a location on a solid-state memory device that is accessible by an address translator module, the address translator module and the solid-state memory device located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.

Claims

1. A computer program product comprising:

a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising;

computer readable program code configured for;

establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board, the solid-state storage devices including a plurality of physical memory locations identified by physical addresses, and the establishing performed externally to the solid-state storage board;

accepting, by the solid-state storage board, the correspondence between the first logical address and the first physical address;

storing the correspondence between the first logical address and the first physical address in a location on a solid-state memory device that is accessible by an address translator module, the address translator module and the solid-state memory device located on the solid-state storage board; and

translating the first logical address to the first physical address, the translating by the address translator module and based on the previously established correspondence between the first logical address and the first physical address.

2. The computer program product of claim 1, wherein the solid-state storage devices include flash memory devices.

3. The computer program product of claim 1, wherein the translating is performed in response to receiving a request to read data, the request including the first logical address, and the method further includes retrieving data from the first physical address.

4. The computer program product of claim 1, wherein the solid-state storage board in coupled to a main board via an interface bus.

5. The computer program product of claim 4, wherein the main board is located on a host computer.

6. The computer program product of claim 1, wherein the establishing a correspondence between the first logical address and the first physical address is responsive to a write request that includes the first logical address and write data, and the method further comprises writing the write data in the solid-state storage devices into a physical location identified by the first physical address.

7. The computer program product of claim 1, wherein the establishing a correspondence between the first logical address and the first physical address is responsive to at least one of a measurement of wear of at least one of the solid-state storage devices, a projected performance of a main board coupled to the solid-state storage board via an interface bus, and characteristics of at least one of the solid-state storage devices.

8. The computer program product of claim 1, wherein the establishing a correspondence between the first logical address and the first physical address is responsive to a prior output of an error correction code (ECC) decoder.