MEMORY SYSTEM

• US 20140136772A1
• Filed: 01/23/2014
• Published: 05/15/2014
• Est. Priority Date: 03/01/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: YANO, Junji, MATSUZAKI, Hidenori, HATSUDA, Kosuke
• Granted Patent: US 9,021,190 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

According to one embodiment, a memory system includes a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and a controller configured to control data stored in the nonvolatile semiconductor memory, wherein the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data.

Claims

1-19. -19. (canceled)

20. A memory system comprising:

a nonvolatile semiconductor memory including a first area being configured to be accessed by a first command, and a second area being configured not to be accessed by the first command; and

a controller configured to control data stored in the nonvolatile semiconductor memory, wherein

when receiving the first command, the controller compresses a data of the first area within the second area and initializes a management information related the first data.

21. A memory system comprising:

a nonvolatile semiconductor memory; and

a controller configured to control data stored in the nonvolatile semiconductor memory, wherein

the nonvolatile semiconductor memory is configured to store a first data accessible by a first command, and the nonvolatile semiconductor memory is configured to store a second data inaccessible by the first command, and

when receiving the first command, the controller compresses the second data of the first area within the second area and initializes a management information related the first data.

22. The memory system according to claim 21, further comprising a volatile semiconductor memory in communication with the nonvolatile semiconductor memory, wherein

the controller is configured to read out at least one part of the management table into the volatile semiconductor memory and to perform the management of data while updating the management table stored in the volatile semiconductor memory, and

when receiving the first command from the host apparatus, the controller initializes the management table stored in the volatile semiconductor memory and writes the initialized management table in the nonvolatile semiconductor memory.

23. The memory system according to claim 22, wherein the nonvolatile semiconductor memory is configured to store a plurality of management tables,

the plurality of management tables include a first management table that records management information including storage positions of data stored in the volatile semiconductor memory and a second management table that records management information including storage positions of data stored in the nonvolatile semiconductor memory, and

when receiving the first command from the host apparatus, the controller initializes the second management table stored in the volatile semiconductor memory and writes the initialized second management table in the nonvolatile semiconductor memory.

24. The memory system according to claim 23, wherein the controller initializes, when receiving the first command from the host apparatus, a section corresponding to the first logical addresses in the second management table.

25. The memory system according to claim 24, wherein the controller does not initialize, when receiving the first command from the host apparatus, a section corresponding to the second logical addresses in the second management table.

26. The memory system according to claim 21, wherein the controller associates SMART (Self-Monitoring, Analysis and Reporting Technology) information with the second logical addresses.

27. The memory system according to claim 21, wherein the nonvolatile semiconductor memory is a NAND flash memory.

28. The memory system according to claim 21, wherein when receiving the first command from the host apparatus, the controller erases data associated with the first logical addresses in the nonvolatile semiconductor memory.

29. The memory system according to claim 21, wherein the controller determines whether it is necessary to collect data associated with the second logical addresses.

30. The memory system according to claim 21, wherein the volatile semiconductor memory is a DRAM.

31. A memory system comprising:

a nonvolatile semiconductor memory including a first area being configured to be accessed by a first command, and a second area being configured not to be accessed by the first command; and

a controller configured to compress a data in the second area on the basis of the first command.