ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE

• US 20140136927A1
• Filed: 10/26/2011
• Published: 05/15/2014
• Est. Priority Date: 10/27/2010
• Status: Abandoned Application

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Li, Yan, Zhong, Hao, Danilak, Radoslav, Cohen, Earl T
• Application Number:
  US13/879,383
• Publication Number:
  US 20140136927A1
• Time in Patent Office: Days
• US Class Current: 714/768
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence

Abstract

Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time.

Claims

1. A system, comprising:

means for error statistics collecting and tracking enabled to dynamically determine a raw Bit Error Rate (BER) of accesses to a portion of a flash memory; and

means for adaptive encoding enabled to encode according to a dynamically selected one of a plurality of error correcting codes, and further enabled to dynamically determine the dynamically selected error correcting code based at least in part on the raw BER.

2. The system of claim 1, wherein encoding according to a first one of the error correcting codes results in a number of error correcting bits to store in the portion that is less than when encoding according to a second one of the error correcting codes.

3. The system of claim 2, wherein when encoding according to the first error correcting code, a number of bits of the portion used as user data is increased by up to a difference between the number of error correcting bits used by the second error correcting code minus the number of error correcting bits used by the first error correcting code.

4. The system of claim 2, wherein when encoding according to the second error correcting code, a number of bits of the portion used as user data is decreased by up to a difference between the number of error correcting bits used by the second error correcting code minus the number of error correcting bits used by the first error correcting code.

5. The system of claim 2, wherein the means for adaptive encoding is further enabled to select the first error correcting code during a first part of a lifetime of the portion and to select the second error correcting code during a second part of the lifetime;

and the second part is after the first part.

6. The system of claim 2, wherein one or more of the means for error statistics collecting and tracking, and the means for adaptive encoding, are implemented at least in part via hardware logic circuitry and/or one or more software routines.

7. A system, comprising:

means for error statistics collecting and tracking enabled to dynamically determine a raw Bit Error Rate (BER) of accesses to a portion of a flash memory; and

means for adaptive encoding/decoding comprising means for adaptive encoding and means for adaptive decoding, the means for adaptive encoding enabled to encode according to a first selected one of a plurality of error correcting codes, the means for adaptive decoding enabled to decode according to a second selected one of the error correcting codes, and the means for adaptive encoding/decoding further comprising means for controlling enabled to determine the first selected error correcting code based at least in part on information received from the means for error statistics collecting and tracking.

8. The system of claim 7, wherein the means for adaptive encoding is a means for universal encoding enabled to encode according to any of the error correcting codes.

9. The system of claim 7, wherein the means for adaptive decoding is a means for universal decoding enabled to decode according to any of the error correcting codes.

10. The system of claim 7, wherein encoding according to the first selected error correcting code results in a number of error correcting bits to store in the portion that is less than when encoding according to the second selected error correcting code.

11. The system of claim 10, wherein when encoding according to the first selected error correcting code, a number of bits of the portion used as user data is increased by up to a difference between the number of error correcting bits used when encoding according to the second selected error correcting code minus the number of error correcting bits used when encoding according to the first selected error correcting code.

12. The system of claim 10, wherein when encoding according to the second selected error correcting code, a number of bits of the portion used as user data is decreased by up to a difference between the number of error correcting bits used when encoding according to the second selected error correcting code minus the number of error correcting bits used when encoding according to the first selected error correcting code.

13. The system of claim 10, wherein the means for adaptive encoding is further enabled to select the first selected error correcting code during a first part of a lifetime of the portion and to select the second selected error correcting code during a second part of the lifetime;

and the second part is after the first part.

14. The system of claim 7, wherein one or more of the means for error statistics collecting and tracking, and the means for adaptive encoding/decoding, are implemented at least in part via hardware logic circuitry and/or one or more software routines.

15. A system, comprising:

means for dynamic code rate selection enabled to dynamically determine a respective code rate associated with each of a plurality of portions of a flash memory;

means for encoding operable according to the respective determined code rates;

means for decoding operable according to the respective determined code rates; and

wherein a particular one of the portions is written with data encoded by the means for encoding according to a particular one of the respective determined code rates, and is subsequently read from the particular portion and decoded by the means for decoding.

16. The system of claim 15, wherein the means for dynamic code rate selection is enabled to dynamically determine the respective code rate based at least in part on one or more parameters per one or more of the portions, or one or more histories of one or more of the parameters, the parameters comprising

a number of errors corrected,

a number of errors detected,

a number of program/erase cycles,

a number of read cycles,

a program time,

an erase time,

a read time,

a temperature, and

a threshold voltage.

17. The system of claim 15, wherein the dynamic determination comprises a determination of a relatively lower code rate to associate with a first one of the portions relatively early in a lifetime of the first portion, and a determination of a relatively higher code rate to associate with the first portion relatively late in the lifetime.

18. The system of claim 17, wherein when encoding according to the relatively lower code rate, a number of bits of the first portion used as user data is greater than when encoding according to the relatively higher code rate.

19. The system of claim 15, wherein one or more of the means for dynamic code rate selection, the means for encoding, and the means for decoding, are implemented at least in part via hardware logic circuitry and/or one or more software routines.