HIGH EFFICIENCY LIGHT EMITTING DIODE

• US 20140138729A1
• Filed: 11/20/2013
• Published: 05/22/2014
• Est. Priority Date: 11/21/2012
• Status: Active Grant

• Current Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Inventors: KIM, Da Hye, You, Jong Kyun, Kim, Chang Yeon, Im, Tae Hyuk
• Granted Patent: US 9,306,120 B2
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating

Abstract

A method of fabricating method light-emitting diode according to an exemplary embodiment of the present invention includes forming a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a first substrate, forming a second substrate on the second conductivity-type semiconductor layer, separating the first substrate from the first conductivity-type semiconductor layer, forming a mask pattern including a plurality of openings on the first conductivity-type semiconductor layer exposed after separating the substrate, etching the first conductivity-type semiconductor layer having the mask pattern disposed thereon to form a plurality of recesses separated from each other, removing the mask pattern, and etching a surface of the first conductivity-type semiconductor layer to form a sub-micro texture.

Claims

1. A method of fabricating a light-emitting diode, the method comprising:

forming a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a first substrate;

forming a second substrate on the second conductivity-type semiconductor layer;

separating the first substrate from the first conductivity-type semiconductor layer;

forming a mask pattern comprising a plurality of openings on the first conductivity-type semiconductor layer exposed after the first substrate is separated;

etching the first conductivity-type semiconductor layer having the mask pattern disposed thereon to form a plurality of recesses separated from each other;

removing the mask pattern;

etching a surface of the first conductivity-type semiconductor layer to form a sub-micro texture; and

forming a passivation layer on the first conductivity-type semiconductor layer, the active layer, and the second conductivity-type semiconductor layer,

wherein the passivation layer is formed in the recesses and on a surface of the sub-micro texture, and comprises a gently inclined surface relative to the surface of the sub-micro texture.

2. The method of claim 1, wherein the mask pattern comprises masking regions surrounding the openings and connected to each other.

3. The method of claim 2, wherein the mask pattern comprises a photoresist.

4. The method of claim 1, wherein the mask pattern comprises hexagonal openings.

5. The method of claim 1, wherein the first conductivity-type semiconductor layer having the mask pattern disposed thereon is etched by dry etching.

6. The method of claim 5, wherein dry etching the first conductivity-type semiconductor layer forms a plurality of micro-conical recesses on the first conductivity-type semiconductor layer.

7. The method of claim 6, wherein each micro-conical recess of the plurality of micro-conical recesses comprises a circular or hexagonal inlet.

8. The method of claim 6, wherein the sub-micro texture comprises sub-micro cones.

9. The method of claim 8, wherein the sub-micro cones are formed between the recesses on the surface of the first conductivity-type semiconductor layer.

10. The method of claim 9, wherein the passivation layer comprises at least one conical portion arranged on the sub-micro cones, the at least one conical portion comprising a gentler slope than the sub-micro cones.

11. The method of claim 1, wherein etching the surface of the first conductivity-type semiconductor layer to form the sub-micro texture comprises using photo-enhanced chemical (PEC) etching.

12. The method of claim 1, further comprising forming a bonding layer on the second conductivity-type semiconductor layer, and bonding the second substrate to the bonding layer.

13. The method of claim 12, further comprising forming an insulating pattern layer on a first region of the second conductivity-type semiconductor layer, before bonding the second substrate.

14. The method of claim 13, further comprising:

forming a reflective metal layer on a second region of the second conductivity-type semiconductor layer; and

forming a barrier metal layer on the reflective metal layer,

wherein the reflective metal layer is coplanar with the insulating pattern layer.

15. The method of claim 13, further comprising:

forming an electrode on a surface of the first conductivity-type semiconductor layer opposite the second substrate,

wherein the electrode is formed on a region arranged directly above the insulating pattern layer.

16. The method of claim 15, wherein the electrode comprises an electrode pad and an electrode extension extending from the electrode pad.

17. The method of claim 12, wherein the second substrate is bonded by eutectic bonding.

18. The method of claim 1, further comprising:

etching the first conductivity-type semiconductor layer, the active layer, and the second conductivity-type semiconductor layer to form a plurality of light emitting elements.

19. The method of claim 8, wherein each of the micro-conical recesses comprises a gentler side slope relative to a side slope of the sub-micro cones.

20. The method of claim 19, wherein the micro conical recesses comprise a U-shape cross-section and the sub-micro cones comprise an inverted V-shape cross-section.

21. A light-emitting diode, comprising:

a second conductivity-type semiconductor layer disposed on a support substrate;

a first conductivity-type semiconductor layer disposed on the second conductivity-type semiconductor layer;

an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer; and

a passivation layer disposed on the first conductivity-type semiconductor layer, the second conductivity-type semiconductor , and the active layer,

wherein the first conductivity-type semiconductor layer comprises a plurality of recesses spaced apart from each other and a sub-micro texture disposed between the recesses on a surface of the first conductivity-type semiconductor layer opposite to the first substrate, and

wherein the passivation layer disposed on the first conductivity-type semiconductor layer is disposed in the recesses and on a surface of the sub-micro texture, the passivation layer comprising a more gently inclined surface relative to the surface of the sub-micro texture.

22. The light-emitting diode of claim 21, wherein the recesses are spaced apart from each other, and regions between the recesses are connected to each other.

23. The light-emitting diode of claim 21, wherein the sub-micro texture comprises sub-micro cones.

24. The light-emitting diode of claim 21, wherein the passivation layer comprises at least one conical portion disposed on the sub-micro cones, the at least one conical portion comprising a gentler slope than the sub-micro cones.

25. The light-emitting diode of claim 23, wherein the recesses comprise micro-conical recesses.

26. The light-emitting diode of claim 25, wherein each of the micro-conical recesses comprises a circular or hexagonal inlet.

27. The light-emitting diode of claim 23, wherein the sub-micro cones comprise an average height of 0.5 μ

m or less.

28. The light-emitting diode of claim 21, further comprising an insulating pattern layer disposed on a first region of the support substrate.

29. The light-emitting diode of claim 28, further comprising a metal layer disposed between the second conductivity-type semiconductor layer and the support substrate.

30. The light-emitting diode of claim 29, wherein the metal layer comprises a reflective metal layer and a barrier metal layer,

wherein the reflective metal layer is disposed on a second region of the support substrate, the barrier metal layer is disposed between the reflective metal layer and the insulating pattern layer and the support substrate, and the reflective metal layer and the insulating pattern layer are disposed on the barrier metal layer.

31. The light-emitting diode of claim 28, further comprising an electrode disposed on the first conductivity-type semiconductor layer,

wherein the electrode is disposed on a region arranged directly above the insulating pattern layer.

32. The light-emitting diode of claim 31, wherein the electrode comprises an electrode pad and an electrode extension extending from the electrode pad.

33. The light-emitting diode of claim 29, further comprising a bonding layer disposed between the support substrate and the metal layer.

34. The light-emitting diode of claim 25, wherein each micro conical recess comprises a gentler side slope than a side slope of the sub-micro cones.

35. The light-emitting diode of claim 34, wherein the micro conical recesses comprise a U-shape cross-section and the sub-micro cones comprise an inverted V-shape cross-section.