INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE

• US 20140138779A1
• Filed: 11/20/2012
• Published: 05/22/2014
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Cai, Xiuyu, Zhang, Xunyuan
• Granted Patent: US 9,190,486 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

Claims

1. A method for fabricating an integrated circuit comprising:

forming a sacrificial gate structure over a semiconductor substrate;

forming a spacer around the sacrificial gate structure;

depositing a dielectric material over the spacer and semiconductor substrate;

selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material, wherein the trench is bounded by a trench surface; and

depositing a replacement spacer material along the trench surface and merging an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

2. The method of claim 1 further comprising:

etching a portion of the merged upper region of the replacement spacer material and exposing the sacrificial gate structure;

removing the sacrificial gate structure to form an opening adjacent the replacement spacer material; and

forming a replacement gate structure in the opening.

3. The method of claim 2 further comprising forming a contact to a source/drain region, wherein the replacement spacer material is between the replacement gate and the contact.

4. The method of claim 2 wherein forming the replacement gate structure comprises:

depositing a high-k dielectric material in the opening along the replacement spacer material and the semiconductor substrate; and

depositing metals in the opening overlying the high-k dielectric material.

5. The method of claim 2 further comprising:

recessing an upper portion of the replacement gate structure to form a recess;

depositing a gate cap material in the recess; and

forming a self-aligned contact adjacent the replacement spacer material.

7. The method of claim 1 further comprising forming a source/drain region aligned with the spacer after forming the spacer around the sacrificial gate structure.

8. The method of claim 1 wherein depositing a replacement spacer material along the trench surface comprises conformally depositing a nitride along the trench surface.

9. The method of claim 1 wherein depositing a replacement spacer material along the trench surface comprises conformally depositing a material having a dielectric constant of no more than about 7 along the trench surface.

10. The method of claim 1 wherein depositing a replacement spacer material along the trench surface comprises conformally depositing SiCBN or SiCN along the trench surface.

11. The method of claim 1 wherein depositing a replacement spacer material along the trench surface comprises conformally depositing the replacement spacer material along a surface of the sacrificial gate structure and a surface of the dielectric material.

12. A method for fabricating an integrated circuit comprising:

forming a sacrificial gate structure over a semiconductor substrate;

depositing a spacer material adjacent the sacrificial gate structure and enclosing a void within the spacer material to form a hollow spacer;

removing the sacrificial gate structure to form an opening adjacent the hollow spacer; and

forming a replacement gate structure in the opening.

13. The method of claim 12 further comprising defining a trench adjacent the sacrificial gate structure, and wherein depositing a spacer material adjacent the sacrificial gate structure comprises depositing a spacer material in the trench.

14. The method of claim 13 wherein defining a trench adjacent the sacrificial gate structure comprises:

forming a sacrificial spacer around the sacrificial gate structure;

depositing a dielectric material over the sacrificial spacer and semiconductor substrate; and

removing the sacrificial spacer to form the trench between the sacrificial gate structure and the dielectric material.

15. The method of claim 14 wherein depositing a spacer material adjacent the sacrificial gate structure and enclosing a void within the spacer material to form a hollow spacer comprises conformally depositing a nitride in the trench.

16. The method of claim 14 wherein depositing a spacer material adjacent the sacrificial gate structure and enclosing a void within the spacer material to form a hollow spacer comprises conformally depositing a material having a dielectric constant of no more than about 7 in the trench.

17. The method of claim 14 wherein depositing a spacer material adjacent the sacrificial gate structure and enclosing a void within the spacer material to form a hollow spacer comprises conformally depositing SiCBN or SiCN in the trench.

18. The method of claim 14 wherein depositing a spacer material adjacent the sacrificial gate structure and enclosing a void within the spacer material to form a hollow spacer comprises depositing a spacer material along a surface of the sacrificial gate structure and a surface of the dielectric material.

19. The method of claim 12 further comprising:

recessing an upper portion of the replacement gate structure to form a recess;

depositing a gate cap material in the recess; and

forming a self-aligned contact adjacent the hollow spacer.

20. An integrated circuit comprising:

a semiconductor substrate;

a gate structure formed on the semiconductor substrate;

a hollow spacer formed around the gate structure and enclosing a void; and

a contact via self-aligned with the hollow spacer.