RAIL-TO-RAIL CONSTANT TRANSCONDUCTANCE DIFFERENTIAL INPUT STAGE

• US 20140139017A1
• Filed: 07/02/2013
• Published: 05/22/2014
• Est. Priority Date: 11/16/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Alex, Saju Mathew
• Granted Patent: US 9,520,849 B2
• Time in Patent Office: Days
• US Class Current: 307/11
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

A primary differential input pair of transistors and a secondary differential input pair of transistors are capable of operating in parallel to provide load current. A level-shifting pre-stage to the secondary differential pair downwardly level-shifts rail-to-rail input signals. Doing so prevents the secondary differential pair from entering cut-off. A tail current shunt device provides tail current to the secondary differential pair as the primary differential pair approaches cut-off when a common-mode component of the input signals approaches the positive voltage rail. Consequently, the sum of currents through first differential input transistors associated with the primary and secondary differential input pairs remains constant to the first load. Likewise, the sum of currents through the second differential input transistors associated with the primary and secondary differential input pairs remains constant to the second load. Both arms of the composite differential input stage present constant transconductances to their respective loads as a result.

Claims

1. A differential input apparatus, comprising:

a tail-connected primary differential pair to receive first and second input signals and to pass load current to first and second loads responsive to the first and second input signals, respectively; and

a tail-connected secondary differential pair to receive downward level-shifted versions of the first and second input signals, at least one of the primary or secondary differential pair to conduct current as a common-mode component of the first and second input signals approaches a positive voltage rail such as to present a constant transconductance in series with each of the first and second loads.

2. The differential input apparatus of claim 1, further comprising:

a tail current source communicatively coupled to the primary and secondary differential pairs, conduction by the primary and secondary differential pairs to prevent linear region operation at the tail current source.

3. The differential input apparatus of claim 2, further comprising:

a tail current shunt device in series between the tail current source and the secondary differential pair, the tail current shunt device to supply tail current to the secondary differential pair as the first and second input signals approach a positive voltage rail and as the primary differential pair approaches a cut-off condition.

4. The differential input apparatus of claim 3, further comprising:

first and second level-shifting devices coupled to inputs associated with the secondary differential pair to provide the downward level-shifted versions of the first and second input signals; and

a bias element coupled to the tail current shunt device to bias and enable the tail current shunt device to conduct when the first level-shifting device enters a conduction state.

5. The differential input apparatus of claim 4, the first and second level-shifting devices being source follower stages.

6. A differential input apparatus, comprising:

a tail-connected primary differential pair of transistors, first and second transistors of the primary differential pair current channel coupled in series with first and second loads, respectively, to receive first and second input signals at first and second gates, respectively, of the primary differential pair of transistors and to pass load current to the first and second loads responsive to the first and second input signals; and

a tail-connected secondary differential pair of transistors, first and second transistors of the secondary differential pair current channel-coupled in series with the first and second loads, respectively, to receive downward level-shifted versions of the first and second input signals at first and second gates, respectively, of the secondary differential pair of transistors, the secondary differential pair to conduct current responsive to the downward level-shifted versions of the differential input signals as the primary differential pair of transistors approaches a cut-off condition such as to present a constant transconductance to the first and second loads as a common-mode component of the first and second input signals approaches a positive voltage rail.

7. The differential input apparatus of claim 6, further comprising:

a tail current source transistor communicatively coupled between a positive voltage rail and current channels associated with the primary and secondary differential pairs to provide tail current to the primary and secondary differential pairs.

8. The differential input apparatus of claim 7, further comprising:

a bias voltage source coupled to the tail current source transistor to provide a bias voltage to a gate of the tail current source transistor and to establish a maximum tail current magnitude.

9. The differential input apparatus of claim 7, further comprising:

a tail current shunt transistor channel-coupled in series between the tail current source transistor current channel and the current channels of the first and second transistors of the secondary differential pair, the tail current shunt transistor to supply tail current to the secondary differential pair as the primary differential pair approaches the cut-off condition.

10. The differential input apparatus of claim 7, further comprising:

a first source follower transistor output-coupled to a gate of the first transistor of the secondary differential pair to receive the first input signal at a gate of the first source follower transistor and to generate the downward level-shifted version of the first signal at the gate of the first transistor of the secondary differential pair; and

a second source follower transistor output-coupled to a gate of the second transistor of the secondary differential pair to receive the second input signal at a gate of the second source follower transistor and to generate the downward level-shifted version of the second signal at the gate of the second transistor of the secondary differential pair.

11. The differential input apparatus of claim 10, further comprising:

a first constant current source coupled in series between a source terminal of the first source follower transistor and at least one of a ground rail or a negative voltage rail to provide a current load to the first source follower transistor; and

a second constant current source coupled in series between a source terminal of the second source follower transistor and at least one of the ground rail or the negative voltage rail to provide a current load to the second source follower transistor.

12. The differential input apparatus of claim 10, further comprising:

a diode-connected transistor current channel-coupled in series between a positive voltage rail and the first source follower transistor and gate-coupled to a gate of the tail current shunt transistor to enable the tail current shunt transistor by pulling the gate of the tail current shunt transistor low when the first source follower transistor enters a conduction state.

13. A method of providing a constant-transconductance electronic differential input stage, comprising:

receiving a first input signal approaching a positive voltage rail at a first gate associated with a first transistor of a tail-connected primary differential pair of transistors;

receiving a second input signal approaching the positive voltage rail at a second gate associated with a second transistor of the tail-connected primary differential pair of transistors;

decreasing current flow from a tail current source transistor through the primary differential pair, resulting in an increased voltage potential at a tail node associated with the primary differential pair; and

providing a tail current to first and second transistors associated with a secondary differential pair of transistors in order to maintain a constant first transconductance in series with a first load associated with the first transistors of the primary and secondary differential pairs and to maintain a constant second transconductance in series with a second load associated with the second transistors of the primary and secondary differential pairs as a common-mode component of the first and second input signals approaches the positive voltage rail.

14. The method of claim 13, further comprising:

biasing the first and second transistors associated with the primary and secondary differential pairs, respectively, in a weak inversion mode.

15. The method of claim 13, further comprising:

receiving the first input signal approaching the positive voltage rail at a gate of a first source-follower transistor output-coupled to a gate of the first transistor of the secondary differential pair; and

receiving the second input signal approaching the positive voltage rail at a gate of a second source-follower transistor output-coupled to a gate of the second transistor of the secondary differential pair.

16. The method of claim 15, further comprising:

biasing the first source-follower transistor using a first constant-current source in series between a source terminal of the first source-follower transistor and at least one of a ground rail or a negative voltage rail; and

biasing the second source-follower transistor using a second constant-current source in series between a source terminal of the second source-follower transistor and the ground rail or the negative voltage rail.

17. The method of claim 15, further comprising:

conducting current through the first source-follower transistor, resulting in a decreased voltage at a positive terminal of a current channel associated with the first source-follower transistor and a bias toward conduction at a gate of a tail current shunt transistor gate-coupled to the positive terminal of the current channel associated with the first source-follower transistor and channel-coupled in series between a current channel of the tail current source transistor and current channels of the first and second transistors associated with the secondary differential pair.

18. The method of claim 17, further comprising:

forward-biasing the current channel of the tail current shunt transistor using the increased voltage potential of the tail node associated with the primary differential pair, the tail node coupled to a positive terminal of the current channel of the tail current shunt transistor.

19. The method of claim 18, further comprising:

receiving a downward level-shifted version of the first input signal at a gate of the first transistor of the secondary differential pair of transistors, the first transistor of the secondary differential pair having a load in common with the first transistor of the primary differential pair of transistors; and

receiving a downward level-shifted version of the second input signal at a gate of a second transistor of the secondary differential pair of transistors, the second transistor of the secondary differential pair having a load in common with the second transistor of the primary differential pair.

20. The method of claim 19, further comprising:

conducting a constant current through the first load from at least one of the first transistor of the primary differential pair or the first transistor of the secondary differential pair; and

conducting a constant current through the second load from at least one of the second transistor of the primary differential pair or the second transistor of the secondary differential pair.