SYSTEMS, APPARATUS, AND METHODS FOR PROVIDING CONTINUOUS-TIME SIGNAL DIFFERENTIATION AND INTEGRATION

• US 20140139280A1
• Filed: 11/18/2013
• Published: 05/22/2014
• Est. Priority Date: 11/20/2012
• Status: Abandoned Application

• Current Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Original Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Inventors: TSIVIDIS, Yannis
• Application Number:
  US14/082,945
• Publication Number:
  US 20140139280A1
• Time in Patent Office: Days
• US Class Current: 327/261
• CPC Class Codes: H03K 2005/00078 Fixed delay
• CPC Class Codes: H03K 2005/0015 Layout of the delay element
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

The disclosed subject matter includes an apparatus. The apparatus is configured to provide an approximate differentiation of an input continuous-time signal. The apparatus includes a continuous-time delay block configured to receive the input continuous-time signal and to delay the input continuous-time signal by a predetermined delay factor to generate a delayed input continuous-time signal; a processing block configured to determine a difference between the input continuous-time signal and the delayed input continuous-time signal; and a multiplication block configured to multiply the difference by a multiplication factor to provide the approximate differentiation of the input continuous-time signal.

Claims

1. An apparatus configured to provide an approximate differentiation of an input continuous-time signal, the apparatus comprising:

a continuous-time delay block configured to receive the input continuous-time signal and to delay the input continuous-time signal by a predetermined delay factor to generate a delayed input continuous-time signal;

a processing block configured to determine a difference between the input continuous-time signal and the delayed input continuous-time signal; and

a multiplication block configured to multiply the difference by a multiplication factor to provide the approximate differentiation of the input continuous-time signal.

2. The apparatus of claim 1, wherein the multiplication factor is an inverse of the predetermined delay factor.

3. The apparatus of claim 1, wherein the continuous-time delay block comprises a delay line.

4. The apparatus of claim 3, wherein the delay line comprises a plurality of delay stages each configured to provide a fixed amount of delay.

5. The apparatus of claim 4, wherein each delay stage comprises at least one inverter.

6. The apparatus of claim 1, wherein the input continuous-time signal is presented using a plurality of continuous-time binary bit signals, and wherein the continuous-time delay block comprises a plurality of sub-blocks operating in parallel, each of which is configured to delay one of the plurality of continuous-time binary bit signals by the predetermined delay factor.

7. The apparatus of claim 6, wherein the processing block comprises an adder implemented using asynchronous logic.

8. An apparatus configured to provide an approximate integration of an input continuous-time signal, the apparatus comprising:

a multiplication block configured to multiply the input continuous-time signal by a multiplication factor to provide an amplitude-adjusted input signal;

a continuous-time delay block configured to receive a first value of an output signal of the apparatus corresponding to the first time instance and provide, at an output of the continuous-time delay block, the first value at a second time instance later than the first time instance; and

a processing block configured to receive, at the second time instance, the amplitude-adjusted input signal from the multiplication block and the first value of the output signal from the output of the continuous-time delay block, and to provide a summation of the amplitude-adjusted input signal and the first value of the output signal to generate a second value of the output signal of the apparatus corresponding to the second time instance, wherein the second value of the output signal is the approximate integration of the input continuous-time signal at the second time instance.

9. The apparatus of claim 8, wherein the multiplication factor is an inverse of the predetermined delay factor.

10. The apparatus of claim 8, wherein the continuous-time delay block comprises a delay line.

11. The apparatus of claim 10, wherein the delay line comprises a plurality of delay stages each configured to provide a fixed amount of delay.

12. The apparatus of claim 11, wherein each delay stage comprises at least one inverter.

13. The apparatus of claim 8, wherein the input continuous-time signal is represented using a plurality of continuous-time binary bit signals, and wherein the continuous-time delay block comprises a plurality of sub-blocks operating in parallel, each of which is configured to delay one of the plurality of continuous-time binary bit signals by the predetermined delay factor.

14. The apparatus of claim 13, wherein the processing block comprises an adder implemented using an asynchronous logic circuit.

15. The apparatus of claim 13, wherein the multiplication block comprises a multiplier implemented using an asynchronous logic circuit.

16. A system comprising:

an apparatus configured to provide an approximate differentiation of an input continuous-time signal, the apparatus comprising;

a multiplication block configured to multiply the input continuous-time signal by a multiplication factor to provide a first signal;

a continuous-time delay block configured to receive the first signal and to delay the first signal by a predetermined delay factor to generate a second signal;

a processing block configured to receive the first signal and the second signal, and to determine a difference between the first signal and the second signal to provide the approximate differentiation of the input continuous-time signal.

17. The system of claim 16, further comprising a controller configured to determine the predetermined delay factor for the continuous-time delay block and to instruct the continuous-time delay block to delay the first signal by the predetermined delay factor.

18. The system of claim 17, wherein the controller is further configured to determine that the multiplication factor is an inverse of the predetermined delay factor and to instruct the multiplication block to multiply the input continuous-time signal by the multiplication factor.

19. The system of claim 16, wherein the input continuous-time signal is presented using a plurality of continuous-time binary bit signals, and wherein the continuous-time delay block comprises a plurality of sub-blocks operating in parallel, each of which is configured to delay one of the plurality of continuous-time binary bit signals by the predetermined delay factor.

20. The system of claim 19, further comprising a continuous-time logic block, in communication with the apparatus, configured to receive the approximate differentiation of the input continuous-time signal to process the approximate differentiation of the input continuous-time signal.