Depth Buffering

• US 20140139524A1
• Filed: 11/20/2012
• Published: 05/22/2014
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nilsson, Jim K., Akenine-Moller, Tomas G.
• Granted Patent: US 9,665,973 B2
• Time in Patent Office: Days
• US Class Current: 345/422
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/405 using Z-buffer

Abstract

In accordance with some embodiments, depth values may be split into more and less significant bits. By so doing, some processing can be done based only on the more significant bits. Where the number of more significant bits is significantly less than the total number of bits, some memory bandwidth can be preserved. In other words, by only using the more significant bits for some of the depth buffering operations, memory bandwidth usage can be reduced, improving efficiency.

Claims

1. A method comprising:

splitting bits making up a depth value in a graphics processing unit into more and less significant bits; and

initially doing a depth buffering analysis only using the more significant bits.

2. The method of claim 1 including only using the less significant bits if the depth analysis with the more significant bits is indeterminant.

3. The method of claim 1 including performing a less than depth test.

4. The method of claim 1 including detecting whether the depth test is determinant using the less significant bits.

5. The method of claim 4 including, if not, performing no memory update.

6. The method of claim 4 including, if so, writing the less significant bits to a cache.

7. The method of claim 6 including not storing the more significant bits.

8. The method of claim 1 including using eight bits of the depth value as the more significant bits.

9. One or more non-transitory computer readable media storing instructions executed by a processor to perform a sequence comprising:

splitting bits making up a depth value in a graphics processing unit into more and less significant bits; and

initially doing a depth buffering analysis only using the more significant bits.

10. The media of claim 9 further storing instructions to perform the sequence including only using the less significant bits if the depth analysis with the more significant bits is indeterminant

11. The media of claim 9 further storing instructions to perform the sequence including performing a less than depth test.

12. The media of claim 9 further storing instructions to perform the sequence including detecting whether the depth test is determinant using the less significant bits.

13. The media of claim 12 further storing instructions to perform the sequence including, if not, performing no memory update.

14. The media of claim 9 further storing instructions to perform the sequence including, if so, writing the less significant bits to a cache.

15. The media of claim 14 further storing instructions to perform the sequence including not storing the more significant bits.

16. The media of claim 9 further storing instructions to perform the sequence including using eight bits of the depth value as the more significant bits.

17. A graphics processing unit comprising:

a core to split depth value bits into a first group of more significant bits and a second group of less significant bits and then to analyze depth buffering using only the first group; and

a memory coupled to said core.

18. The unit of claim 17 said core to use the less significant bits of the depth analysis with the more significant bits is indeterminant.

19. The unit of claim 17 said core to detect whether the depth test is determinant using the less significant bits.

20. The unit of claim 19, if not, said core to perform no memory update.

21. The unit of claim 19, if so, said core to write the less significant bits to a cache.

22. The unit of claim 21 said core to not store the more significant bits.

23. The unit of claim 17 said core to use eight bits of the depth value as the more significant bits.

24. The unit of claim 17 said core to perform a less than depth test.

25. The unit of claim 17 including an operating system.

26. The unit of claim 17 including a battery.

27. The unit of claim 17 including firmware and a module to update said firmware.