IMAGING DEVICE

• US 20140139712A1
• Filed: 11/25/2013
• Published: 05/22/2014
• Est. Priority Date: 05/31/2011
• Status: Abandoned Application

• Current Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Yamamoto, Takahiro, MATSUNAGA, Yoshiyuki, YARINO, Makoto
• Application Number:
  US14/088,514
• Publication Number:
  US 20140139712A1
• Time in Patent Office: Days
• US Class Current: 348/296
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14669 Infrared imagers
• CPC Class Codes: H04N 2101/00 Still video cameras
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

An imaging device includes: a stack-type solid-state imaging device which includes pixels including: a photoelectric conversion film which performs photoelectric conversion on light to convert the light into signal charges; a pixel electrode on a first surface of the photoelectric conversion film, the first surface being at a side of the semiconductor substrate; a transparent electrode on a second surface of the photoelectric conversion film, the second surface being opposite to the first surface; and a pixel circuit unit configured to read the signal charges, and accumulate the read signal charges, and the imaging device further includes a control unit configured to control exposure time by selectively applying, to the transparent electrode, a voltage having a first voltage value at which the signal charges move to the pixel circuit unit and a voltage having a second value at which the signal charges move to the pixel circuit unit.

Claims

1. An imaging device comprising

a stack-type solid-state imaging device including a plurality of pixels arranged in a matrix above a semiconductor substrate,

wherein each of the pixels includes:

a photoelectric conversion film which is formed above the semiconductor substrate and performs photoelectric conversion on light to convert the light into signal charges;

a pixel electrode formed on a first surface of the photoelectric conversion film, the first surface being at a side of the semiconductor substrate;

a transparent electrode formed on a second surface of the photoelectric conversion film, the second surface being opposite to the first surface; and

a pixel circuit unit configured to read the signal charges generated through the photoelectric conversion by the photoelectric conversion film via the pixel electrode, and accumulate the read signal charges,

the imaging device further comprising

a control unit configured to control exposure time by selectively applying, to the transparent electrode, a voltage having a first voltage value at which the signal charges generated through the photoelectric conversion by the photoelectric conversion film move to the pixel circuit unit and a voltage having a second voltage value at which the signal charges do not move to the pixel circuit unit.

2. The imaging device according to claim 1,

wherein the control unit is configured to perform:

exposure start control for starting exposure by switching from the voltage having the second voltage value to the voltage having the first voltage value to be applied to the transparent electrode; and

exposure end control for ending the exposure by switching from the voltage having the first voltage value to the voltage having the second voltage value to be applied to the transparent electrode, after the exposure start control, and

the pixel circuit unit is configured to read the signal charges generated through the photoelectric conversion by the photoelectric conversion film during an exposure period starting when the exposure start control is performed and ending when the exposure end control is performed, and accumulate the read signal charges.

3. The imaging device according to claim 2,

wherein the control unit is further configured to perform read control for sequentially reading signal charges accumulated in a plurality of the pixel circuit units included in the respective pixels, after the exposure end control.

4. The imaging device according to claim 3,

wherein the pixel circuit unit is connected to the pixel electrode, and includes:

a first electric charge accumulation unit configured to accumulate the signal charges;

a second electric charge accumulation unit; and

a transfer transistor formed between the first electric charge accumulation unit and the second electric charge accumulation unit, and

in the read control, the control unit is configured to;

apply the voltage having the second voltage value to the transparent electrode and switch ON the transfer transistor to transfer the signal charges accumulated in the first electric charge accumulation unit to the second electric charge accumulation unit; and

sequentially read, from the pixels, signals according to signal charges accumulated in a plurality of the second electric charge accumulation units.

5. The imaging device according to claim 2,

wherein the control unit is further configured to perform reset control for (i) applying the voltage having the second voltage value to the transparent electrode, before the exposure start control, and (ii) resetting signal charges accumulated in a plurality of the pixel circuit units, before the exposure start control.

6. The imaging device according to claim 5,

wherein the control unit is further configured to perform the reset control, after the read control.

7. The imaging device according to claim 5,

wherein the pixel circuit unit includes a reset transistor for resetting the signal charges accumulated in the pixel circuit unit, and

in the reset control, the control unit is configured to reset the signal charges accumulated in the pixel circuit unit by switching ON the reset transistor using a tapered signal.